International Business Machines Corporation

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Infineon Technologies Ag

Infineon Technologies North America Corp.

Alan C Thomas

Alois Gutmann

Gerhard Kunkel

Zhijian Lu

Perry G Hartswick

John T Federico

Margaret C Lawson

Kuang Jung Chen

Qinghuang Lin

Yann Mignot

Ravikumar Ramachandran

Chi-Chun Liu

Pai-Hung Pan

Albert Manhee Chu

Daniel Sanders

Dario Leonardo Goldfarb

Rajasekhar Venigalla

Nelson M Felix

Kafai Lai

Chandrasekhar Narayan

Christopher Joseph Waskiewicz

John Christopher Arnold

Christopher P Ausschnitt

Timothy A Brunner

Henning Haffner

Kevin J Stewart

Shahid Ahmad Butt

Axel Christoph Brintzinger

Donald J Samuels

Scott Josef Bukofsky

John W Golz

Thomas S Rupp

Franz X Zach

Teresa Jacqueline Wu

Robert A Coles

Juergen Preuninger

Kevin M Golden

David Thomas Jewett

Fred L Einspruch

Anne Marie Pelella

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

Fabricating tapered semiconductor devices

An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

Embedded etch rate reference layer for enhanced etch time precision

A system and method for determining the position of people and/or objects, whether mobile or stationary, is presented herein. The system uses fixed and/or portable FM transmitters to transmit synchronized signals. These signals are acquired by a Receiver device which uses the signal timing to perform Time Difference of Arrival calculations to determine the Receiver's location. Then, using some arbitrary communications method, such as wireless communications, the Receiver device can forward its location to some arbitrary type of application system.

Method and apparatus for location determination of people or objects

A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of incidence with respect to a surface of the photolithographic mask. The photolithographic mask includes a substantially transparent mask substrate and one or more lines and spaces patterns formed on the mask substrate and having a periodicity P. The mask substrate includes at least one phase shifting region. At least part of the light that is transmitted through the photolithographic mask is collected using one or more projection lenses which project the portion of the transmitted light onto the material substrate. The material substrate is disposed substantially parallel with, but at a distance from, a focal plane of the projection lens system. The phase shifting region of the mask substrate and the distance from the focal plane are selected such that a substantially focused image is projected onto the material substrate that includes the lines and spaces patterned but with a periodicity P/2.

Method of reducing pitch on semiconductor wafer

A method for employing a plurality of reusable reticles in an integrated circuit manufacturing process employing lithographic exposure of a semiconductor wafer. Initially there is provided a matrix of a plurality of reticles, each matrix comprising a plurality of tuples of reticles, each reticle tuple comprising one or more reticles. The method then includes defining at least one set of valid groups of reticles in the matrix for use in a desired lithographic exposure process, defining a set of conditions for determining availability of all reticles in the valid groups in the lithographic exposure process, and comparing the availability conditions to the reticles in the set of valid groups and eliminating valid groups which do not meet the availability conditions, leaving non-eliminated valid groups. The method also includes defining a set of conditions for determining priority of all reticles in the non-eliminated valid groups in the lithographic exposure process, comparing the priority conditions to the reticles in the set of valid groups and ranking non-eliminated valid groups according to the priority conditions, and selecting for use in the lithographic exposure process reticles from the non-eliminated valid groups according to ranking by the priority conditions.

Reticle exposure matrix

A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Stepper-framing-blades are moved over the dead zone to prevent additional exposures after an initial exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position.

Plural interleaved exposure process for increased feature aspect ratio in dense arrays

A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 &mgr;m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Method of using optical proximity effects to create electrically blown fuses with sub-critical dimension neck downs

A system is provided for controlling the time at which a durable item, such as a reticle used in a lithography process in semiconductor manufacturing, is requalified for use. A counting device counts occurrences of predefined events, such as the number of jobs in which the reticle is used or the number of times it is placed in a lithography tool. The reticle is not removed from use until a limiting number of jobs or tool placements is reached, or the reticle is needed for processing the requalification job. The system also includes a requalification device for the durable item.

Requalification controller for durables

In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50% of the dose-to-clear for a non-patterned exposure.

Method of reducing post-development defects in and around openings formed in photoresist by use of non-patterned exposure

In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable remnants (denoted as Blob Defects) of various components of photoresist material remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of using a Puddle Development technique to develop the photoresist material, and subsequently exposing the semiconductor wafer to at least one Puddle Rinse cycle which uses water.

Method of reducing post-development defects in and around openings formed in photoresist by use of multiple development/rinse cycles

A method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. A selected material layer having an affinity to a resist coat to be applied over the selected material layer is applied to a wafer having a plurality of recesses before applying a resist coat. After the resist coat is applied over the selected material layer, the selected material diffuses partially into the resist coat to condition a portion of the resist coat to be insoluble in the presence of a developer which is applied after the resist coat. Those portions of the resist coat into which the selected material layer has not diffused then are removed by a developer leaving a uniform resist coat thickness across the wafer.

Method for resist filling and planarization of high aspect ratio features

The present invention provides a method and an optical lithographic system which eliminates the standing wave effect typically observed in photoresists without the need for altering the thickness of the photoresist, utilizing an anti-reflective coating material, or changing the light source. Specifically, the present invention compensates for standing waves by exposing the photoresist with light from a light source at different phases. That is, in the present invention there is a change in light exposure from a single dose at one phase to a plurality of doses at different phases; therefore dispersing the effects of the standing wave at each of those phases which in turn eliminates the standing wave.

Elimination of standing waves in photoresist

A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.

Contact and deep trench patterning

Focus and exposure parameters may be controlled in a lithographic process for manufacturing microelectronics by creating a complementary tone pattern of shapes and spaces in a resist film on a substrate. Corresponding dimensions of the resist shape and space are measured and the adequacy of focus or exposure dose are determined as a function of the measured dimensions. Etching parameters may also be controlled by creating a complementary tone pattern of etched shapes and spaces on a substrate. Corresponding dimensions of the etched shape and space are measured and the adequacy of etching parameters are determined as a function of the measured dimensions.

Optically measurable serpentine edge tone reversed targets

A trench capacitor with a buried plate is formed with a single etching process by the expedient of filling the trench so formed and lined with diffusion source material with resist by baking and reflowing the resist which also serves to adjust exposure sensitivity of the resist such that exposure and development of the resist removes the resist to a repeatable and uniform depth. Remaining resist allows etching of the diffusion source layer to a very accurate dimension. Thus only a readily formed oxide or TECS layer is needed to confine impurities during diffusion to form the buried plate. An isolation collar can be formed after recess of the fill to avoid formation of step corners and erosion of the isolation collar by repeated fill and etch back processes while permitting maximum capacitance to be achieved for a given trench 'footprint'.

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Hughsonville, NY, United States of America

Alan C Thomas