Sony Corporation

Independent Broadcasting Authority

Alan C Thirlwall

John G Ive

A random access memory arrangement for reading data out of and into a random access memory asynchronously, for example, to effect time base correction of a digital television signal, comprises a random access memory having common read and write data terminals, an input circuit for supplying input data to said read and write data terminals for writing in the random access memory, a first output latch circuit connected to the read and write data terminals, a second output latch circuit connected to the first latch circuit, and means for supplying control signals to enable the random access memory to write the input data therein at given addresses in synchronism with write pulses of a write pulse signal, to enable the random access memory to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, the read pulse signal being asynchronous with the write pulse signal, to control the first output latch circuit to hold and to supply to the second output latch circuit data supplied to the first latch circuit immediately prior to each write pulse, and to pass therethrough to the second latch circuit data supplied to the first latch circuit at all other times, and to control the second latch circuit to hold the data supplied to it by the first latch circuit immediately prior to the beginning of each read pulse until the beginning of the next succeeding read pulse and to supply the data so held to an output of the arrangement.

Random access memory arrangements

Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of data blocks, each block formed of N n-bit words and including within each block a predetermined serial group of m bits forming the synchronizing information, which identify each block of information and enable de-serialization of said signal. The apparatus comprises a first m-stage shift register through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, and which supplies a pulse whenever it holds a predetermined serial group of m bits, a frequency divider to derive from the incoming digital signal a word rate clock pulse signal. Additionally, the apparatus comprises an n-stage shift register through which each said pulse is stepped at the bit rate of the incoming digital signal, a latch circuit synchronized with the word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of the shift register, comparators comparing each phase word with at least one other phase word delayed N or an integral multiple of N word periods of an earlier incoming digital signal. Comparators supply a control signal only when at least one of the comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, wherein the position of this bit in the phase words indicates the phasing of the word rate clock pulse signal relative to the words of the incoming digital signal. In addition, circuits are provided to deserialize the incoming digital signal into parallel-bit n-bit words under control of the control signal.

Synchronization word extractor

A circuit for monitoring digital data in the form of words comprising a plurality of digits comprises a shift register through which the digital data is fed and one or more memory devices arranged to compare the data in the shift register with predetermined data stored in the memory device or devices. The memory device or devices produce a numerical count of the number of digits either which are correct or which are incorrect and that number is compared by a comparison circuit with a reference value in order to control dumping or further processing of the data.

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Winchester, United Kingdom

Alan C Thirlwall