University of Notre Dame Du Lac

International Business Machines Corporation

Alan C Seabaugh

Siyuranga O Koswatta

Patrick Fay

Huili (Grace) Xing

Yeqing Lu

Mark A Wistey

Erich Kinder

Cristobal Alessandri

Susan Fullerton

Guangle Zhou

An electronic device can include a semiconductor material including a channel region configured to conduct a current, a source contact electrically coupled to the channel region at a first location, a drain contact electrically coupled to the channel region at a second location spaced apart from the first location, a partial-polarization material on the semiconductor material between the source contact and the drain contact opposite the channel region and a gate contact on the partial-polarization material opposite the channel region and ohmically coupled to the drain contact or ohmically coupled to the source contact.

Partial-polarization resistive electronic devices, neural network systems including partial-polarization resistive electronic devices and methods of operating the same

A single-transistor random access memory (RAM) cell may be used as universal memory. The single-transistor RAM cell generally includes a first gate, a 2D-crystal channel, a source, a drain, an ion conductor, and a second (back) gate. The single-transistor RAM cell is capable of drifting ions towards the graphene channel. The ions in turn induce charge carriers from the source into the graphene channel. The closer the ions are to the graphene channel, the higher the conductivity of the graphene channel. As the ions are spaced from the graphene channel, the conductivity of the graphene channel is reduced. Thus the presence of the charged ions adjacent to the channel is used to modify the channel's conductivity, which is sensed to indicate the state of the memory.

Single transistor random access memory using ion storage in two-dimensional crystals

A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Low voltage tunnel field-effect transistor (TFET) and method of making same

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Notre Dame, IN, United States of America

Alan C Seabaugh