Texas Instruments Corporation

Other

Alan C Seabaugh

Gary A Frazier

Edward A Beam, Iii

Chih-Chen Cho

Robert M Wallace

John Neal Randall

Han-Tzong Yuan

Andrew J Purdes

Yung-Chung Kao

James M Beggs

Harold H Hosack

Robert J Mattauch

James H Luscombe

Yung Chung Kao

Hung-Yu Lin

Chad H Mikkelson

A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Nanomechanical switches and circuits

A quantum transistor (,) includes an emitter (,), an injector structure (,), a base (,) and a collector (,) coupled to the base. The injector (,) is interposed between the emitter (,) and the base (,). The injector structure (,) includes a quantum well (,) having a general conductance band minimum energy level. A notch (,) in the well (,) has a conductance band minimum energy level that is lower than the general level. This notch (,) is operable to lower the energy of electrons disposed in the quantum well (,). Therefore, the electrons resident in the well are injected through a barrier (,) into the base (,) at an energy level at or slightly above the base/collector barrier &phgr;,, but below the X or L energies such that intervalley scattering is reduced.

Hot carrier transistors utilizing quantum well injector for high current gain

A method of fabricating a quantum well device is presented which includes forming one or more quantum wells 48 by forming an epitaxy mask followed by selective deposition of one or more epitaxial layers. Selective deposition is accomplished by forming an epitaxy mask by sidewall defined masking, followed by epitaxial deposition of one or more layers (e.g. barrier layers 40 and 44 and a quantum layer 42) The epitaxy mask is formed by patterning an e-beam resist layer (e.g. polymethylmethacrylate 36), conformally depositing a glass layer (e.g. SiO.sub.2 38) on the resist, anisotropically etching the SiO.sub.2, and then removing the e-beam resist layer. The epitaxy mask fabrication technique allows patterning to define geometries that are much smaller than the beam itself and thereby provides the means required to define nanometer dimensioned horizontal (lateral) structures on and within epitaxial layers.

Method of forming lateral resonant tunneling devices

A multiple peak resonant tunneling diode (10) includes multiple vertical semiconductor structures (12, 13). The vertical structures (12, 13) include a resonant tunneling diode having a predetermined cross-sectional area and a series resistor of a predetermined resistance. The vertical structures (12, 13) are spaced from one another and interconnected in parallel. Additionally, the vertical semiconductor structures (12, 13) are fabricated such that their predetermined diode cross-sectional areas and series resistances have values that vary by predetermined amounts to adjust the respective peak currents and/or peak voltages of the vertical semiconductor structures (12, 13).

Multiple peak resonant tunneling diode

A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height.

Silicon resonant tunneling

A solid-state frequency multiplier circuit (10) is provided which includes a bipolar quantum-well resonant tunneling transistor (12), a resistive load (14), and an A.C. output coupling capacitor (16), all which may be formed in a single integrated circuit or as discrete components. The value of the resistive load (14) determines the frequency multiplication factor of the circuit (10), and can produce frequencies in a range from about 2 GHz to over 20 GHz. A different embodiment of the present invention provides a frequency multiplication circuit (20) which generates a sinusoidal output waveform, without using an output A.C. coupling capacitor.

Bipolar resonant tunneling transistor frequency multiplier

A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Mixed barrier resonant tunneling

A magnetic sensor using heterojunction transistors for detecting magnetically recorded data. The sensor has a pair of heterojunction transistors T1, T2 connected in a differential circuit disposed on a substrate 18. The substrate 18 is carded on the free end of a suspension arm 12 at a distance D from the surface of a disk 14 having magnetically recorded data thereon. The transistors are disposed a distance S apart which is selected with D so that the magnetic field direction at one transistor is generally perpendicular to the disk 14 and the magnetic field direction at the other transistor is generally parallel to the disk 14 when a magnetic transition occurs immediately adjacent the magnetic sensor.

Magnetic field sensor using heterojunction bipolar transistors

A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height, and the openings (430) have an irregular (nonperiodic) shape.

Silicon oxide resonant tunneling diode structure

A multi-function resonant tunneling logic gate is provided in which a resonant tunneling transistor (12) includes a first terminal, a second terminal, and a third terminal. A plurality of signal inputs are coupled to the first terminal of the resonant tunneling transistor (12) through a summer (10). Furthermore, a biasing input is operable to apply a bias to the first terminal of resonant tunneling transistor (12) such that the transfer characteristic of the resonant tunneling transistor (12) can be shifted relative to the signal inputs.

Multi-function resonant tunneling logic gate and method of performing

This is a method of generating noise comprising the step of switching a plurality of resonant tunneling diodes each located in the emitter or base of a multi finger transistor such that each of the resonant tunneling diodes switches at a different input voltage. Other devices and methods are also disclosed.

Resonant tunneling transistor noise generator

This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Integrated field effect transistor and resonant tunneling diode

This is a vertical field-effect resonant tunneling transistor device comprising: a semi-conducting substrate 46; a drain region 48 above the semi-conducting substrate; a multiple-barrier multi-well resonant tunneling diode 52, 54, 56, 58, 60 above the drain layer; a two dimensional electron gas heterostructure 64 above the multiple-barrier multi-well resonant tunneling diode; a source region 72 extending through the two dimensional electron gas and above the multiple-barrier multi-well resonant tunneling diode; ohmic contacts 70 on the source region, wherein the source region provides an ohmic connection to the two dimensional electron gas; and gate s! 68, 74 besides the source region.

Growing community of inventors

Richardson, TX, United States of America

Alan C Seabaugh