Sun Microsystems, Inc.

International Business Machines Corporation

Alan C Folta

Trung Minh Tran

Sze Tom

Paul Gerard Villarrubia

Sharad Mehrotra

Parsotam Trikam Patel

Disclosed are novel methods and apparatus for reorganizing data in a log file. In an embodiment, a method of reorganizing data in an original log file is disclosed. The method includes: obtaining a data record from the original log file; examining the data record; if the data record includes a single-value entry, inserting the data record in a single-value storage linked list; if the data record includes a multiple-values entry, inserting the data record in a multiple-values linked list; and utilizing data from the multiple-values and single-value linked lists to write data to a new log file.

Reorganizing data in log files for data tracking management

Disclosed are novel methods and apparatus for manipulating and generating a real-time counter in network computing environments. In an embodiment, a method of tracking a defect is disclosed. The method includes providing a defect abstract, the defect abstract including information to identify the defect; identifying a component having the defect; assigning a user to resolve the defect; and assigning a defect number to identify the defect, the defect number obtained by incrementing a counter value stored in a file, the file being accessible by a single user at a time.

Defect tracking by utilizing real-time counters in network computing environments

A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area. By utilizing these recorded information, the parasitic capacitance of the integrated circuit can be estimated more efficiently.

Growing community of inventors

Austin, TX, United States of America

Alan C Folta