Analog Devices International Unlimited Company

Alan Brannick

Edward John Coyne

Shane Patrick Geary

Catriona Marie O'Sullivan

Shane Tooher

Breandán Pol Og Ó hAnnaidh

John P Meskell

Breandán Pol Og ÓhAnnaidh

A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.

Bipolar junction transistor, and a method of forming an emitter for a bipolar junction transistor

A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.

High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region

A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.

Bipolar junction transistor, and a method of forming a collector for a bipolar junction transistor

A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

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Auburn Hills, MI, United States of America

Alan Brannick