International Business Machines Corporation

Globalfoundries Inc.

Alan Bernard Botula

Alvin Jose Joseph

James Albert Slinkman

Randy Lee Wolf

Yun Shi

Theodore Gerard Van Kessel

Max L Lifson

Mark David Jaffe

Richard A Phelps

Edward J Nowak

Robert Mark Rassel

Michel J Abou-Khalil

Max Gerald Levy

John J Ellis-Monaghan

James Stuart Dunn

Mark E Stidham

Steven H Voldman

Theodore James Letavic

Gerd Pfeiffer

Jeffrey P Gambino

John Joseph Pekarik

Stephen Ellinwood Luce

Renata A Camillo-Castillo

Howard Smith Landis

Peter James Lindgren

David S Collins

David T Hui

BethAnn Rainey

Dale Warner Martin

Dinh Dang

Beth Ann Rainey

Douglas Brian Hershberger

Jeffrey E Hanrahan

Anthony K Stamper

Steven M Shank

William F Clark, Jr

Daniel Scott Vanslette

Alan D Norris

Blaine Jeffrey Gross

Michael Lawrence Gautsch

Alan Frederick Norris

Kenneth F McAvey

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Integrated circuit heat dissipation using nanostructures

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

SOI-MOSFET gate insulation layer with different thickness

A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

Field effect transistor and method of manufacture

An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

Silicon-on-insulator heat sink

Approaches for body contacted transistors are provided. A method of manufacturing a semiconductor structure includes forming a field effect transistor (FET) including a channel and a gate. The method also includes forming a diode that is electrically connected between the channel and the gate, wherein the diode and channel are contained in a same layer of material.

Diode biased body contacted transistor

A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Forming structures on resistive substrates

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Essex Junction, VT, United States of America

Alan Bernard Botula