Intel Corporation

Alan Beecher Kyker

Stavros Kalafatis

Darrell D Boggs

Robert F Krick

Robert D Fisch

Chan W Lee

Reynold V D'Sa

Per H Hammarlund

Hitesh Ahuja

Joseph F Rohlman

William Alexander

Rebecca E Hebda

Bret L Toll

Stephan Jourdan

Stephen H Gunther

Jonathan M Eastep

Richard J Greco

Federico Ardanaz

Ramkumar Nagappan

David M Lee

Jonathan P Douglas

Michael D Upton

James D Allen

David W Burns

Gustavo P Espinosa

Michael C Rifani

Alan S Geist

Slade A Morgan

Robert B Chaput

Gad Shlomo Sheaffer

Scott Dion Rodgers

Nicholas G Samra

Donald D Parker

Roshan J Fernando

Richard A Weier

Shlomit Weiss

Gad S Sheaffer

Vihang D Pandya

James Allen

Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

Systems and methods for synergistic software-hardware power budget management

Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

Data transfer between asynchronous clock domains

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

System and method for storing immediate data

The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.

Detection, recovery and prevention of bogus branches

A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Updating stack pointer based on instruction bit indicator without executing an update microinstruction

In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Determining whether thread fetch operation will be blocked due to processing of another thread

A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

Method and apparatus for power mode transition in a multi-thread processor

A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.

Method and apparatus for thread switching within a multithreaded processor

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.

Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction

A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor

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Portland, OR, United States of America

Alan Beecher Kyker