Other

Integrated Systems

Alan Bawden

W Daniel Hillis

Thomas F Knight, Jr

David Monroe Chapman

Carl R Feynman

Lowell S Gilbert

Cliff A Lasser

Brewster L Kahle

S Robert Austein

Shawn A Routhier

David P Christman

A standard SNMP management station is replaced by a client computer having a standard Web browser while utilizing the services of a Web/SNMP proxy agent in accordance with the present invention. The Internet locations of the ASN.1 specifications for various MIB modules, as well as other information resources associated with those MIB modules, are stored in resource records in a section of the DNS established for storing such information. The Web/SNMP proxy agent automatically locates the ASN.1 specification for each MIB module of any identified SNMP agent, by looking up the location in the DNS. The Web/SNMP proxy agent then compiles the ASN.1 MIB module specifications into HTML documents for viewing on the client computer. User requests for retrieving data from specified MIB objects and/or for sending data values to specified MIB objects are communicated from the client computer to the Web/SNMP proxy agent using standard HTTUP communications. When the specified SNMP agent is remotely located from the Web/SNMP proxy agent, the Web/SNMP proxy agent converts the user requests into SNMP packets that are communicated to the specified SNMP agent. SNMP reply packets are converted into HTML documents, generally by inserting the information in the reply packets into previously generated HTML MIB specification documents, that are then communicated back to the user's client computer.

Computer network system and method using domain name system to locate

A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith. Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.

Parallel processor/memory circuit

Growing community of inventors

Cambridge, MA, United States of America

Alan Bawden