International Business Machines Corporation

Alain R Gach

Michel H Peyronnenc

Michel L Costes

Yves Hartmann

Jean-Pierre C Dugre

An adapter No (n-1) propagates a daisy-chained grant signal directly to the adapter No (n) and a by-passed grant signal to the adapter No (n+1) case. The adapter No (n) is responsive to the status of the previous adapter in the chain, for determining which of the regular grant signal ('GR') or by-passed grant signal ('GRA') has to be taken account of by the succeeding adapter, when the latter wants to access the transmission bus (11). Further, the adapters connected to the chain may be partitioned into groups (80) within which the grant signal is distributed in parallel to the adapters, and propagated to the next group only when none of its adapters (10) requests access to the transmission bus. The same priority level is given to each adapter or group of adapters connected to the daisy-chain, and permits said chain to remain operative even when several adapters are unplugged or malfunction.

System for selectively detecting and bypassing inoperative module within

An interface mechanism is described for controlling the exchange of information between two devices, such as a direct memory access controller 12 and adapter 5 through bus 10. The exchange is initiated by the adapter which activates the request line 44 and read/write signal on line 62 indicating whether a memory read or write operation is requested. The controller sends back a grant signal on line 46 when the request may be serviced. Ready line 60 is monitored and checked by the adapter and valid line 52 is monitored and checked by the controller. Turn around signal on line 64 controls the direction of the transfer on bidirectional data lines 66. A write or read operation begins with the transmission by the adapter of control parameters (address and byte count). Then for a write operation, the data burst is sent from the adapter to the controller and for a read operation the data burst is sent from the controller to the adapter. The sampling clock always travels with the parameters and data. Controller 12 transmits data with a clock 28 used by the adapter to sample that data and adapter transmits data with a clock 36 used by the controller 12 to sample that data. Clock 36 is generated by inverting clock 28. Thus the bus presents the advantages of synchronous and asychronous modes of operation. The data exchanges are synchronous, so that no time is wasted in handshaking protocols. Because of its asynchronous nature between transfers, the bus is independent of the controller data handling scheme, memory type and memory access time.

System with plural clocks for bidirectional information exchange between

The memory control subsystem controls and arbitrates access to a memory shared by a plurality of users. A processor with its cache and input/output devices has direct access to the memory through a direct memory access bus. The controls subsystem comprises a processor controller, a DMA controller and a memory controller. A processor request is buffered into the processor controller and is serviced immediately if the memory controller is available. A simultaneous transfer between the devices and buffers in the DMA controller is possible. If the memory controller is busy, the DMA controller causes the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards. Write requests made by the processor are buffered into processor controller and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion. A read request which does not hit the cache is sent to the processor controller which causes the cache to be updated. In case of multiple processor requests contending with a long DMA transfer, the latter is sliced into several parts, each part mapping one cache line. In case of a DMA write, the cache lines which correspond to memory positions whose content is modified by the write operation are invalidated in such a way that the processor cannot read a partially written line into the cache.

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Vence, France

Alain R Gach