International Business Machines Corporation

Alain Pinzaglia

Alain R Blanc

Patrick J Jeanniot

Sylvie Gohl

Menahem Kaplan

A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.

System for checking data integrity in a high speed packet switching network node

A Switch Fabric system comprising at least one Switch Fabric subsystem ( ) further including a set of Switch cores elements ( ) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters ( ) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core ( ) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.

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St. Laurent du Var, France

Alain Pinzaglia