Cypress Semiconductor Corporation

Silicor Materials Inc.

Intel Corporation

Cypress Semiconductor Company

Alain Paul Blosse

Krishnaswamy Ramkumar

Kamel Ounadjela

Mira Ben-Tzur

Fritz Kirscht

Martin Kaes

Fuad Badrieh

Peter G Borden

Sundar Narayanan

Jianmin Qiao

Yitzhak Gilboa

Andreas Kraenzl

Omar Sidelkheir

Sanjay Thedki

Allen McTeer

James A Hunter

Bill Phan

Manuj Rathor

Sanjay M Thekdi

Matthias Heuer

Mehran G Sedigh

Prabhuram Gopalan

Saurabh Dutta Chowdhury

Jean Patrice Rakotoniaina

Anis Jouini

Mark Meldrim

Marcin Walerysiak

Renhua Zhang

Dutta Saurabh Chowdhury

John Gorman

A polarization resistant solar cell using an oxygen-rich interface layer is provided. The oxygen-rich interface layer may be comprised of SiON, which may have a graded profile that varies between oxygen-rich proximate to the solar cell to nitrogen-rich distal to the solar cell. A silicon oxide passivation layer may be interposed between the solar cell and the SiONgraded dielectric layer. The graded SiONdielectric layer may be replaced with a non-graded SiONdielectric layer and a SiN AR coating.

Polarization resistant solar cell design using an oxygen-rich interface layer

A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.

Quality control process for UMG-SI feedstock

A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. The back surface includes a doped region, the doped region having the same conductivity as the substrate but with a higher doping level. Contact grids are formed, for example by screen printing. Front junction isolation is accomplished using a laser scribe.

Bifacial solar cells with back surface doping

A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. After removing the PSG, assuming phosphorous diffusion, and isolating the front junction, dielectric layers are deposited on the front and back surfaces. Contact grids are formed, for example by screen printing. Prior to depositing the back surface dielectric, a metal grid may be applied to the back surface, the back surface contact grid registered to, and alloyed to, the metal grid during contact firing.

Bifacial solar cells with overlaid back grid surface

A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a Pregion and an Nregion.

Gate stack having nitride layer

Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Seed layer for reduced resistance tungsten film

A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Method for cleaning a gate stack

A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Method of patterning elements within a semiconductor topography

In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Increasing self-aligned contact areas in integrated circuits using a disposable spacer

In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.

Method of selective tungsten deposition on a silicon surface

A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Nitride layer on a gate stack

A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.

Selective oxidation of gate stack

A method of forming a semiconductor structure comprises forming sidewall oxide on a stack, by rapid thermal oxidation. The stack is on a substrate and comprises (i) a first layer comprising silicon, (ii) a second layer, comprising silicon and tungsten, on the first layer, and (iii) a capping layer, on the second layer. The sidewall oxide in contact with the second layer is at most 50% thicker than the sidewall oxide in contact with the first layer.

Poly/silicide stack and method of forming the same

In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Integrated circuit with improved RC delay

A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.

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Belmont, CA, United States of America

Alain Paul Blosse