Other

Centre National Detudes Spatiales

Safran Data Systems

Zodiac Data Systems

Alain M Thomas

Michel Servel

Nicolas Pasternak

Jean-Pierre Millerioux

Xavier C Maitre

Adrien Gay

Mathieu Llauro

Stanislas Augarde

Youcef Sini

Andre Helen

Jean-Marc Leveau

Emmanuel Bouisson

Clément Dudal

Method for processing a sequence of digital signal samples including a first sub-sequence and a second sub-sequence. Forming a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence. Demodulating the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols. The second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples, which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence. Reconstructing a sequence of symbols by concatenating the first symbol block with the second symbol block.

Method for demodulating digital signals using multiple digital demodulators

A method of date-stamping reception of digital data of a signal coherently modulating the carrier or sub-carrier, and utilizing the properties of such a modulation to improve the date-stamping thereof. Thereby accurately correcting the date-stamping of a pilot sequence (known pattern), and reducing the variance on the date-stamping of the transitions of the bits.

Method of date-stamping telemetry signals

The invention relates to a radio communication receiver receiving a radio signal (S) including a main polarisation (MAIN-POL) and a secondary polarisation (X-POL) orthogonal to the main polarisation (MAIN-POL), the receiver including: a unit () for receiving the main polarisation (MAIN-POL) and the secondary polarisation of the received signal, synchronised as a carrier frequency with the main polarisation (MAIN-POL); a unit () for cancelling out the secondary polarisation synchronised with the main polarisation (MAIN-POL) and configured to suppress, from the received signal (S), the interference due to the secondary polarisation (X-POL), the unit () for cancelling out the secondary polarisation including a filtering unit () that receives the main polarisation (MAIN-POL) and the secondary polarisation (X-POL) as input; a unit () for demodulating the filtered signal, located downstream of the cancellation unit and configured to calculate carrier frequency error information and to communicate same by feedback to the upstream receiving unit ().

Radio communication receiver cancelling out the cross polarisation of a received signal

An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.

Asynchronous FIFO device comprising a stack of registers having a

The method consists in converting an inputting multiframe including of M frames each having words assigned respectively to C multiplexed digital channels into an outgoing multiframe including of C packets each having M words of a respective channel. So as to only use a single memory, a word having a given rank in the outgoing multiframe and a word having said given rank in the inputting multiframe are read and written consecutively in a same cell of the single memory. The memory has a capacity at least equal to MC word cells. The MC cells are addressed according to an address order rebecoming identical to itself after a cycle of N multiframe periods, where N is the smallest integer so that C.sup.N .tbd.1 (mod (MC-1)).

Method and device for converting digital channel multiframes into packet

A memory arrangement for temporary data storage of the FIFO type includes a random access memory associated with an input buffer register and two output buffer registers. The registers may consist of transparent flip-flops. The control system for the arrangement is provided for authorizing reading out from the output register at any time independently of the writing times in the random access memory and for causing reading out from the random access memory in response to an indication that the first output register is empty. A priority input of said control system makes it possible to interrupt a reading or writing operation when a request for the other operation is received. The control system has means for detecting full condition and empty condition of the FIFO. The control system further includes a handling logic for the output registers. That handling logic has two flip-flops which respectfully represent the presence of data in the two output registers and a circuit for setting the first flip-flop in response to loading of the first output register during an internal reading cycle in the random access memory and a circuit for emptying the second register and resetting the second flip-flop in response to a reading request by a user.

FIFO arrangement for temporary data storage

The system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of each incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction. Responsive to a signal for indicating that one of the output junctions is enabled, the address contained in the corresponding queue is read, in order to find the output packet which is to be transferred to the outgoing junction in the buffer memory.

(Time division multiplex) switching system for routing trains of

A digital train is synchronized to correct the framing of received information. To this end, the transmitted digital train is timely structured into recurrent time intervals having a fixed length. The information to be transmitted is divided into blocks called packets, having the length of a time interval and comprising a field of data and a header used for identifying the packets. A digital transmission system with a TDM multiplex is divided into equal and recurrent time intervals, wherein the information is indexed by an associated explicit header, and wherein the absence of information in a time interval is indexed by a specific header which is not used elsewhere as a header. The recognition of a specific address is also used for synchronizing the alignment of the time intervals.

Synchronization for a digital train intended for a correct framing of

Transmission system of frequency division multiplex signals on a digital link. At the transmitting end of the digital line, the frequency division multiplex signals are sampled and coded into n-bit sample words. These sample words are transcoded into p-bit on-line words with p smaller than n through a transcoding procedure which makes a plurality k of successive levels of the n-bit code correspond to one and the same level of the p-bit code. The number k is selected depending on the maximal level reached by a sample word in a block of successive sample words. The number k is transmitted to the receiving end of the digital link by a control word for reverse transcoding of the on-line p-bit words into reconstituted n-bit sample words.

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Lannion, France

Alain M Thomas