Intel Corporation

Other

Alain Gravel

Ilango S Ganga

Anil Vasudevan

Robert G Southworth

Jonathan A Dama

Radia Joy Perlman

Thomas D Lovett

Hugh Wilkinson

Greg J Regnier

Karl S Papadantonakis

Jose Niell

Ronen Chayat

Matthew James Webb

Brad Burres

Ben-Zion Friedman

Parthasarathy Sarangam

Sanjeev Jain

Robert G Hathaway

Amit Kumar

Ygdal Naouri

Naru Dames Sundar

Erik A McShane

Nadav Turbovich

Amit Y Kumar

A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.

Cyclic redundancy check (CRC) update mechanism

This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

Ethernet enhancements

CRC update mechanism

Technologies for processing network packets in an agent-mesh architecture include a network interface controller (NIC) of a computing device configured to write, by a network fabric interface of a memory fabric of the NIC, a received network packet to the memory fabric in a distributed fashion. The network fabric interface is configured to send an event message indicating the received network packet to a packet processor communicatively coupled to the memory fabric. The packet processor is configured to read, in response to having received the generated event message, at least a portion of the received network packet from the memory fabric, identify an agent of the NIC for additional processing of the received network packet, generate a network packet received event message indicating the received network packet is available for processing, and transmit the network packet received event message to the identified agent. Other embodiments are described herein.

Technologies for processing network packets in agent-mesh architectures

Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

Technologies for processing network packets by an intelligent network interface controller

Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.

Pipelined hash table with reduced collisions

This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.

One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.

Credit flow control for ethernet

Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

Single-lane, twenty-five gigabit ethernet

An embodiment may include circuitry that may provide, at least in part, at least one indication that at least one portion of data is available for processing by at least one data processor. The at least one indication may be provided, at least in part, prior to the entirety of the at least one portion of the data being available for the processing by the at least one data processor. The at least one data processor may begin the processing in response, at least in part, to the at least one indication. Many alternatives, variations, and modifications are possible.

Growing community of inventors

Thousand Oaks, CA, United States of America

Alain Gravel