Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

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Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

France Telecom

Stmicroelectronics (rousset) Sas

Alain Chantre

Michel Marty

Sébastien Cremer

Pascal Chevalier

Didier Dutartre

Badhise Ben Bakir

Hélène Duprez

Thomas Ferrotti

Charles Baudot

Jean-Pierre Blanc

Jorge Regolini

Bertrand Martinet

H&eacute;l&egrave;ne Baudry

Helene Baudry

S&eacute;bastien Jouan

Didier Celi

Gregory Avenier

Thierry Schwartzmann

Michel Laurens

Jean Du Port De Poncharra

Daniel Bois

Alain Nouailhat

Pierre Llinares

Francois Guette

Augustin Monroy

A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Methods of fabricating integrated circuit devices with components on both sides of a semiconductor layer

The invention relates to a III-V heterostructure laser device () arranged in and/or on silicon, comprising: The optical rib waveguide () is oriented so that at least one Bragg grating () is arranged on that side () of the slab waveguide () which is proximal relative to the gain medium () and in that the rib () is placed on that side () of the slab waveguide () that is distal relative to the gain medium ().

Laser device and process for fabricating such a laser device

A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

Method for making photonic chip with multi-thickness electro-optic devices and related devices

A III-V heterostructure laser device located in and/or on silicon, including a III-V heterostructure gain medium, a rib optical waveguide, located facing the gain medium and including a strip waveguide equipped with a longitudinal rib, the rib optical waveguide being located in the silicon, two sets (RBE-A, RBE-B) of Bragg gratings formed in the rib optical waveguide and located on either side of the III-V heterostructure gain medium, each set (RBE-A, RBE-B) of Bragg gratings including a first Bragg grating (RB1-A, RB1B) having a first pitch and formed in the rib and a second Bragg grating (RB2-A, RB2-B) having a second pitch different from the first pitch and formed on that side of the rib waveguide which is opposite the rib.

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Heterojunction bipolar transistor

A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

Bipolar transistor manufacturing method

A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Method of manufacturing a photonic integrated circuit optically coupled to a laser of III-V material

A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Integrated hybrid laser source compatible with a silicon technology platform, and fabrication process

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, =; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.

Bipolar transistor with high dynamic performances

A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.

Integrated circuit bipolar transistor

A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type; forming a silicon oxide layer; opening a window in the silicon oxide and silicon layers; forming on the walls of the window a silicon nitride spacer; removing the silicon-germanium layer from the bottom of the window; forming in the cavity resulting from the previous removal a heavily-doped single-crystal semiconductor layer of the second conductivity type; and forming in said window the emitter of the transistor.

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Seyssins, France

Alain Chantre