Stmicroelectronics S.a.

Stmicroelectronics Gmbh

Gemalto Sa

Axalto S.a.

Sgs-thomson Microelectronics S.a.

Thales Dis France Sa

Invia Sas

Schlumberger Malco, Inc.

Alain C Pomet

Yannick Teglia

Pierre-Yvan Liardet

Benjamin Duval

Robert A Leydier

Bernard Plessier

Serge F Fruhauf

Fabrice Romain

Fabrice Marinet

Michel Thill

Alexandre Malherbe

Laurent Sourgen

Taylor Jude Leaming, Iii

The invention relates to an electronic circuit for interconnecting a smartcard chip with a peripheral device, comprising: &#x2014;a dedicated communication interface adapted to communicate with a smartcard chip; &#x2014;a configurable communication interface adapted to communicate with a peripheral device; &#x2014;a configuration module adapted to receive on said dedicated communication interface a request for configuring the configurable communication interface, adapted to configure the communication protocol of the configurable communication interface with the peripheral device based on the received request; &#x2014;a bridging module adapted for converting data exchanged between the peripheral device and the smartcard chip through the dedicated communication interface and the configurable communication interface.

Electronic circuit for interconnecting a smartcard chip

A method and a circuit for protecting a digital quantity over a first number of bits, in an algorithm executing at least one modular exponentiation of data by the quantity, the steps including at least one squaring up and at least one multiplication and implementing, for each bit of the quantity, different calculation steps according to the state of the bit, a same number of multiplications being performed whatever the state of the bit and all the calculation steps using a multiplication being taken into account to calculate a final result.

Protection of a calculation performed by an integrated circuit

A bridge circuitis provided between first data port A, Aand second data port B, B. The bridge circuit comprises a first transceiver stagecomprising at least one input bufferand at least one tri-state output bufferlinked to the first data port, a second transceiver stagecomprising at least one input bufferand at least one tri-state output bufferlinked to the second data port, a first detection circuitfor detecting the arrival of a packet by the first data port, a second detection circuitfor detecting the arrival of a packet by the second data port. A selection circuitryenables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

USB bridge

A method and a circuit for checking the coherence between data read from a first area of a memory of a microcontroller and the address of these data, including calculating a current digital signature of the read data by a function also taking into account the address of these data in the memory, and checking the coherence between the current signature and a previously-recorded signature.

Protection of data of a memory associated with a microprocessor

A method and a circuit for protecting the execution of a program, including initializing at least one counter, carrying on with the normal program execution, interrupting this execution when the counter reaches a given value, and executing at least one integrity check of the calculation after this interrupt.

Protection of the execution of a program executed by an integrated circuit

A method for protecting an execution, by an integrated circuit, of a ciphering and/or deciphering algorithm taking into account data and at least one valid key and performing several iterations of the same calculation, including at least one execution of an iteration with the valid key between several executions of the same iteration with the invalid keys obtained by applying at least one non-linear one-way function to the valid key.

Protection of the execution of a DES algorithm

A method and a circuit for protecting a numerical quantity contained in an integrated circuit on a first number of bits, in a modular exponentiation computing of a data by the numerical quantity, including: selecting at least one second number included between the unit and said first number minus two; dividing the numerical quantity into at least two parts, a first part including, from the bit of rank null, a number of bits equal to the second number, a second part including the remaining bits; for each part of the quantity, computing a first modular exponentiation of said data by the part concerned and a second modular exponentiation of the result of the first by the FIG.exponentiated to the power of the rank of the first bit of the part concerned; and computing the product of the results of the first and second modular exponentiations.

Protection of a modular exponentiation calculation performed by an integrated circuit

A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Method and device for generating a random number in a USB (universal serial bus) peripheral

A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the counter has reached its count, at least one instruction of a secondary program from which the result of the main program depends.

Protection of the execution of a program

One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal &#x3c6;() to &#x3c6;(&#x2212;1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal &#x3c6;() to j(&#x2212;1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal &#x3c6;() to &#x3c6;(&#x2212;1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Method and circuit for local clock generation and smartcard including it thereon

A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.

Secured USB peripheral

A method and a circuit for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, and generating an error signal in case of an identity between the value and the data waiting to be output.

System and method for protection of data contained in an integrated circuit

A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Data communication device

A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.

Protection of the flow of a program executed by an integrated circuit or of data contained in this circuit

An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

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Marseille, France

Alain C Pomet