Sgs-Thomson Microelectronics S.a.

Etat Francais Represente Par Le Ministre Des Postes, Telecommunications

Sgs-Thomson Microelectronics Limited

Alain Artieri

Francis Jutand

Michel Imbert

Jean-Louis Douche

Sylvain Kritter

Joel Cambonie

Phillipe Chaisemartin

A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at '0'. A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.

Dual-port memory

A system for processing compressed data corresponding to pictures includes a decoding mechanism, providing a picture memory with decoded picture data. The decoding mechanism requires, for decoding a current block of a previously decoded picture. A plurality of decoders are associated with respective picture memories, each storing a specific slice of corresponding blocks of a plurality of pictures, as well as at least one margin which is liable to be a predictor block serving to decode a block of the specific slice.

Apparatus and method for decompressing high definition pictures

This MPEG Decoder relates to the decoding of an image that can be of a bi-directional type requiring data from two previously decoded images, each image being displayed in two successive fields corresponding to lines with different parities. Each bi-directional image is decoded twice during its display time, a first time as a first field of the image is being directly displayed, and a second time as the second field is being directly displayed.

MPEG decoder with reduced memory capacity

A system for converting digital television signals encoded according to an MPEG standard into standardized analog video signals. The system includes means for generating graphic images and for inserting corresponding image signals in a decoded digital flow of main image signals, a digital decoding unit, and an analog coding unit. The digital decoding unit includes means for providing a flow of multiplexed image signals including a first flow of main image signals and of a second flow of image signals that contains, in addition to the main image signals, possible graphic image signals. The analog coding unit includes a demultiplexer of the flow of multiplexed image signals and two encoders. The two encoders respectively receive the first and second flows, and each respectively provide a digital flow of images encoded according to a color television standard to digital-to-analog converters respectively associated therewith, the digital-to-analog converters providing the standardized analog video signals.

System for converting digital television signals with insertion of

A system incorporates a processor that includes a data bus having a fixed N-bits size connected to an n-bits word memory through a bus having an n-bits size, where N is a multiple of n, and n is a variable value. The system includes means for, at each execution by the processor of a write instruction of one word of N bits in the memory, successively writing each sub-word of n bits constituting this word of N bits at distinct addresses, and means for, at each execution of a read instruction of a word of N bits in the memory, successively reading in this memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the fixed size bus.

Image processing system including a variable size memory bus

A data reorganization process includes a dual-port memory coupled to a system for writing words in a first predetermined order and for reading the words in a second predetermined order. A register cooperates with the circuit authorizing reading of the words only if the content of the register is non-zero. The content of the register is decremented at each read and incremented at each write. The increment is equal to one plus the difference between the input rank of the current word provided on the first bus and the output rank of this word if the difference is non-negative, and whose value is zero if the difference is negative. The effective value of this increment is such that the sum of the increments that are used until the writing of the current word is written is lower than, or equal to, the sum of the optimum values of these used increments.

System for writing words into memory in first order and concurrently

A pixel matrix filter includes n input buses to receive pixels of n successive columns of the matrix; n delay circuits respectively receiving the pixels from the n input buses, each of these delay circuits introducing a delay of one column, whereby 2n pixels are simultaneously transmitted to the outputs of the n delay circuits and to the n input buses, successively; and n adders connected at least so that the i-th adder receives the i-th of the 2n pixels at a first input and the (i+1)th of the 2n pixels at a second input.

Pixel matrix filter

A processor architecture for executing a current task among a plurality of possible tasks. The architecture includes: a plurality of instruction pointers respectively associated with the tasks and each storing the address of the current instruction to be executed of the associated task, only one of these pointers being enabled at a time to supply an address to the memory; a priority level decoder including circuitry for assigning a predetermined priority level to each request signal and for enabling the instruction pointer associated with the active request signal having the highest priority level; and a mechanism for incrementing the content of the enabled instruction pointer and for reinitializing it at the start address of the associated program when its content reaches the end address of the associated program.

Multitask processor architecture having a plurality of instruction

A system that processes compressed data arriving in packets corresponding to picture blocks, the packets being separated by headers containing decoding parameters of the packets. A memory bus is controlled by a memory controller to exchange data between the processing elements and a picture memory. A pipeline circuit contains a plurality of processing elements. A parameter bus provides packets to be processed to the pipeline circuit, as well as the decoding parameters to elements of the system. The parameter bus is controlled by a variable length decoder that receives the compressed data from the memory bus and that extracts the packets and the decoding parameters therefrom.

Picture processing system

A method for sorting the k greatest ones of a sequence of n incoming data values, by: a) sequentially writing each data value into one of n one-word memories, in a word format which includes, in decreasing weight order, the following bits: a first inhibition bit (MI), a second selection bit (MS), third data bits (MD), and fourth bits (MP) representative of the position of the incoming datum; b) setting the first bits (MI) of the n words during the arrival of the first signal; c) while writing each data value, resetting the first (MI) and second (MS) bits of the corresponding word; and d) between the arrivals of the (n-k).sup.th datum and n.sup.th datum, detecting the smallest word stored in the memories and setting its second bit (MS).

Circuit and a method for selecting the kappa greatest data in a data

A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.

System for rearranging sequential data words from an initial order to an

A device for converting a horizontal scanning of successive lines of N data into a saw tooth scanning of stripes having a height of M lines. This device comprises a MN word memory wherein are sequentially written the first MN data, then wherein the following data are sequentially written while the existing data are read out at same successive addresses A.sub.i,j. The value of i determines the sequence number of the data of the memory (0&lt;i&lt;MN-1), and the value of j determines a stripe number (1&lt;j&lt;n). An address generator supplies addresses A.sub.i,j so that A.sub.i+1,j =(A.sub.i,j +x.sub.j) Modulo(MN-1), x.sub.j being a number such that x.sub.j+1 =N.x.sub.j Modulo(MN-1) and x.sub.j =1.

Device for converting a line scanning into a vertical saw tooth scanning

A circuit for generating non-overlapping complementary clock signals at a double frequency from an input clock signal. An NAND flip-flop (2) has complementary outputs on which double frequency signals are available. A D-type flip-flop (3) receives on its clock input (H) one of the outputs of the NAND flip-flop, and has its output (Q.sub.D) coupled to its data input (D) through an inverter. Two Exclusive OR gates (XO1, XO2) receive on their first inputs the input clock signal and its complement, respectively, and on their second input the output of the D-type flip-flop. The outputs of the OR gates are connected to the inputs (E1 and E2) of the NAND flip-flop, respectively.

Clock frequency doubler

A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

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Meylan, France

Alain Artieri