National Semiconductor Corporation

King Fahd University of Petroleum and Minerals

Alaaeldin A Amin

James Brennan, Jr

Turki Faisal Al-Somani

Muhammad Waleed Shinwari

Bernard Emoto

The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0&#xb7;qq. . . q), then the algorithm provides for computing to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit qusing a quotient digit selection function; (2) generating the product qD; and (3) performing the triple addition of rR, (&#x2212;qD) and where R=bA. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

High-radix multiplier-divider

The method for elliptic curve scalar multiplication may provide several countermeasures to protect scalar multiplication of a private key k by a point P to produce the product kP from power analysis attacks. First, the private key, k, is partitioned into a plurality of key partitions, which are processed in a random order, the resulting points being accumulated to produce the scalar product kP. Second, in each partition, the encoding is randomly selected to occur in binary form or in Non-Adjacent Form (NAF), with the direction of bit inspection being randomly assigned between most-to-least and least-to-most. Third, in each partition, each zero in the key may randomly perform a dummy point addition operation in addition to the doubling operation. The method may be implemented in software, smart cards, circuits, processors, or application specific integrated circuits (ASICs) designed to carry out the method.

Method for elliptic curve scalar multiplication

A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor. A memory cell structure described in accordance with this invention allows a reduction of the portion of the floating gate covering the programmable transistor portion of the channel length. This results in a reduction in the floating gate to substrate capacitance (C.sub.FB) thereby improving the programming coupling ratio and reducing the overall cell size.

Electrically reprogrammable EPROM cell with merged transistor and

A memory circuit incorporates a differential sense amplifier to be utilized in conjunction with a memory array comprised of a plurality of memory cells each containing a single transistor. A high slew rate differential input signal is applied to the sense amplifier based upon the binary data stored in an addressed memory cell. This is accomplished by pre-charging the selected bit line and a reference bit line, and then selecting the word line of the memory cell to be read, while causing the reference memory cell to conduct. The differential voltage between the selected bit line and the reference bit line is then sensed to determine the state of the data stored in the selected memory cell. The ratio of currents through the selected bit line and the reference bit line is selected to be other than one, in order to achieve a rapid differential voltage swing, and rapid reading of the data stored within the selected memory cell.

High speed differential sense amplifier for use with single transistor

An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

Growing community of inventors

Dhahran, Saudi Arabia

Alaaeldin A Amin