Semiconductor Components Industries, LLC

On Semiconductor Trading, Ltd.

Emma Mixed Signal C.v.

Alaa El-Agha

Dustin Griesdorf

Gareth Pryce Weale

Jakob Nielson

Gareth P Weale

Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.

Digital data encoding and decoding method and system

A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Configurable demodulator and demodulation method

A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation. The system for modulation-based commutations link includes a modulation unit having a dividing mechanism for dividing a reference clock by a divide value, and a configuration register for one or more configurable divide sequences.

Growing community of inventors

Waterloo, Canada

Alaa El-Agha