Integrated Device Technology, Inc.

Al Xuefeng Fang

Yue Yu

Chao Xu

Craig DeSimone

YanBo Wang

Roland T Knaack

Tak Kwong Wong

Jon R Williamson

Brian Butka

Liang Leon Zhang

Suresh Atluri

Alan Wolfram Glaser

Mike Farrell

An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.

Asymmetric on-state resistance driver optimized for multi-drop DDR4

An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.

Overvoltage protection circuits and methods of operating same

A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption.

Method and apparatus for a low power AC On-Die-Termination (ODT) circuit

A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.

System and method for testing a clock circuit

A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift unit selects some of the clock signals based on the control signal and generates a feedback signal based on the selected clock signals. The feedback signal has a phase based on the phases of the selected clock signals. The phase locked loop aligns the phase of the feedback signal with the phase of the input signal. In this process, the phase locked loop shifts the phase of each of the clock signals relative to the phase of the input signal.

Multiphase clock generator

Clock generators include phase-locked and delay-locked loop integrated circuits that support efficient high speed testing of clock frequencies. An integrated circuit device is provided with a clock signal generator having at least one delay element therein that is responsive to a control signal. A speed tracking circuit is also provided. This speed tracking circuit is configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of the at least one delay element.

Locked-loop integrated circuits having speed tracking circuits therein

A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal. The phase control circuit may be operative to cause the phase interpolator circuit to shift from one extreme of a delay range thereof towards another extreme of the delay range concurrent with a step change in delay through the variable delay circuit to thereby limit overcompensation.

Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit

Clock recovery circuits and methods include a first phase locked loop that generates a control signal in response to a reference clock. A pulse generating and delaying circuit is responsive to the input data signal to generate from the input data signal pulses of predetermined width that are delayed by a predetermined delay. A second phase locked loop is responsive to the control signal, to the pulse generating and delaying circuit and to a mode signal, to generate a clock signal from the input data signal. Accordingly, only the first phase locked loop need include a reference clock. Moreover, in an integrated circuit that includes multiple data ports, only the pulse generating and delaying circuit and the second phase locked loop may need to be duplicated for each data port, to allow each data port to operate at a frequency that is independent of the other data ports. A common first phase locked loop, including a common reference clock, may provide a common control signal to all data ports.

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Suwanee, GA, United States of America

Al Xuefeng Fang