University of Texas System

Motorola Corporation

Al F Tasch, Jr

Sanjay K Banerjee

Richard A Jones

Alan H Cowley

Qiqing Ouyang

A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.

High mobility heterojunction transistor and method

The present invention involves the use of organocalcium precursors for the chemical vapor deposition of thin CaF.sub.2 films under exceptionally mild conditions. This method is based on utilizing an organocalcium compound and a source of fluorine in a chemical vapor deposition reaction to form CaF.sub.2.

Growth of polycrystalline CaF.sub.2 via low temperature OMCVD

A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared by the cells on either side of it; the bit line on one side of a particular cell being used to write to the cell while the bit line on the other side of the cell is used to read from the cell. This dual use of bit lines, plus the use of a vertical FET transistor along one side of a trench capacitor, plus the avoidance for the need of a relatively large storage capacitor since the cell is not read by 'dumping' or releasing its charge onto the bit line all aid in making this cell compact and suitable for high density memories. Since the substrate serves as the second source/drain region of the vertical FET, a separate line for this region is eliminated, also contributing substantially to a smaller cell size.

Growing community of inventors

Austin, TX, United States of America

Al F Tasch, Jr