Arm Limited

Akshay Kumar

Piyush Agarwal

Azeez Jennudin Bhavnagarwala

Lucian Shifren

Shidhartha Das

Bal S Sandhu

Mudit Bhargava

Glen Arnold Rosendale

El Mehdi Boujamaa

Vivek Asthana

Andy Wangkun Chen

Edward Martin McCombs, Jr

Cyrille Nicolas Dray

Piyush Jain

Bo Zheng

Robert Campbell Aitken

Lalit Gupta

Vivek Nautiyal

Jitendra Dasani

Andreas Hansson

Surya Prakash Gupta

Yew Keong Chong

Andrew David Tune

Sriram Thyagarajan

Sean James Salisbury

Rahul Mathur

Munish Kumar

Ankur Goel

Akash Bangalore Srinivasa

Shruti Aggarwal

Mohit Chanana

Saikat Kumar Banik

Khushal Gelda

Gaurav Kumar

A write circuitry may include a first write driver and at least one additional write driver for a set of bitlines coupled to bitcells of a memory; column select circuitry; a first storage element coupled to an input data pin to receive data for storing in the memory; and at least one additional storage element coupled in series with the first storage element. The first storage element and each of the at least one additional storage element are also coupled to a corresponding write driver. The column select circuitry may include a first column select circuitry for the first write driver that selects from a first subset of the set of bitlines; and a second column select circuitry for a second write driver that selects from a second subset of the set of bitlines, where the first subset and the second subset are overlapping sets.

Column select topology supporting increased throughput for writes to memory

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

Rising edge detection of a closing cycle for a multi-cycle operation

A method for write operations to memory include starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuitry performing the aforementioned operations can also perform write operations for a single word in two clock cycles.

Increased throughput for writes to memory

Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

Multi-port circuit architecture

Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

Bias generation circuitry

Broadly speaking, embodiments of the present techniques provide apparatus and methods for generating a reference current for a memory array sensing scheme, and for using the generated reference current to sense the state of memory cells within the memory array. The generated reference current is particularly suitable for distinguishing between a high resistance state and a low resistance state.

Generating a reference current for sensing

Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

Voltage regulation circuitry

Briefly, embodiments of claimed subject matter relate to circuits and methods for providing signals, such as signals to bring about writing of binary logic values to magnetic random-access memory (MRAM) cells. In particular embodiments, such circuits may operate to control output signal variability over an operating temperature range.

Circuits to control output signal variability

Briefly, the disclosure relates to circuits utilized to perform writing operations to a memory array, in which elements of the array comprise resistive memory cells coupled in series with an access device. In one embodiment, a circuit may comprise a supply voltage coupled to a first side of the array and a current source coupled to a second side of the array. The access devices of the elements of the array may be body-biased, which may operate to reduce the turn-on voltage (V) of the access devices. Particular voltages may be applied to gate regions of the access devices to control leakage current to the resistive memory cells of the array.

Increasing current to memory devices while controlling leakage current

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.

Method, system and device for non-volatile memory device operation

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Power-on-reset circuit

Subject matter disclosed herein may relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.

Controlling current through correlated electron switch elements during programming operations

To sense an impedance state of one or more correlated electron switch elements, a bit-line may be precharged to a voltage level that is less than a precharge voltage level for a sense amplifier, and a bit-line may be discharged through one or more correlated electron switch elements. A bit-line may be buffered from a sense amplifier via an electronic switch device.

Bit-line sensing for correlated electron switch elements

Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analog or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.

Electronic filter circuit

Disclosed are methods, systems and devices for operation of a circuit to boost a voltage at a load for a particular duration. A plurality of capacitors, each capacitor comprising at least a first terminal, may be coupled to an assisted node. At least a first capacitor and a second capacitor of the plurality of capacitors may maintain the assisted node at or about a target voltage for a duration. The second capacitor may be charged while the first capacitor is discharging in at least a portion of the duration.

Growing community of inventors

New Delhi, India

Akshay Kumar