Cadence Design Systems, Inc.

Akshat Shah

Keith Dennison

Prakash Gopalakrishnan

Prakash Krishnan

Jeremiah Cessna

Rongchang Yan

David N Dixon

David Allan White

Michael McSherry

Ed Fischer

Bruce Yanagida

Regis R Colwell

Timothy Rosek

Khaled M Elgalaind

Patrick Hyde

Wilfred Vance Kenzle

A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a first routing trunk along channels in the circuit layout, coupling the first routing trunk to one device of the two devices, and checking that a placement of a plurality of devices and the coupling the first routing trunk to one device of the plurality of devices meet a circuit layout specification. A computer system and a non-transitory computer-readable medium storing commands to execute the above method are also provided.

Method and apparatus for placement and routing of analog components

Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.

Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation

Disclosed are method(s), system(s), and article(s) of manufacture for creating or manipulating electrical data sets for an electronic design across multiple abstraction levels. The method identifies simulation result(s) obtained from simulation run(s) for an electronic circuit or at least a portion thereof, identifies at least a part of one or more sets of simulation results, each of which is obtained from a simulation run for the electronic circuit or at least a portion thereof at the first abstraction level, identify relevant electrical data or information for design under test instance(s) of a master library or a master cell and creates electrical data set(s), generates a view for at least some of the electrical data set(s), and hand-off the electrical data set(s) to second abstraction level. The method may further identify preexisting electrical data set(s). The method may further compare the electrical data set(s) and preexisting electrical data set(s).

Methods, systems, and articles of manufacture for creating or manipulating electrical data sets for an electronic design

Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.

Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness

Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.

Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness

A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy

Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment. In yet other techniques, a user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

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Pittsburgh, PA, United States of America

Akshat Shah