Stmicroelectronics International N.v.

Stmicroelectronics S.r.l.

Akshat Jain

Ranajay Mallik

Saurabh Sona

Tejinder Kumar

Ivan Clemente Massimiani

Giuseppe Catalisano

Luigi Abbatelli

According to an embodiment, an LLC resonant converter includes a switching bridge having a plurality of power switches. The switching bridge is configured to receive a DC voltage input and generate a square waveform based on a pulse-modulated frequency (PFM) signal at the switching bridge. The LLC resonant converter further includes a resonant tank circuit coupled to the switching bridge. The resonant tank circuit includes a resonant inductor. The resonant tank circuit is excited in response to receiving the square waveform. The PFM signal is adjusted such that an elapsed time between a rising edge of a Drain-Source Voltage of a power switch and a zero-crossing point of current flowing through the resonant inductor falls within a predetermined range corresponding to the resonant tank circuit operating at its resonant frequency.

Peak efficiency tracking in an LLC converter of a multi-stage power conversion system

In accordance with various embodiments of the present disclosure, a wireless power transmitter is provided. In some embodiments, the wireless power transmitter comprises an inverter electrically connected to a transmit power coil to receive an alternating current (AC) input voltage and configured to provide power to the transmit power coil to enable wireless power transmission, near field communication (NFC) transmit circuitry electrically connected to and providing power to an NFC transmit coil to enable NFC communication, and a controller electrically connected to the inverter and to the NFC transmit circuitry and configured to disable the inverter from providing power to the transmit power coil and enable the NFC transmit circuitry to provide power to the NFC transmit coil during a plurality of NFC communication time slots. A beginning and an end of each of the NFC communication time slots is determined based on the AC input voltage.

Wireless power transmitter and associated method

A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

LED control and driving circuit capable of both analog and digital dimming

Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

Control circuitry for increasing power output in quasi-resonant converters

A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

Three-phase power factor controller implemented with single-phase power factor correction controller

A circuit includes a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.

A driving circuit including a reference voltage generator to generate a reference voltage based on an operating frequency of a complementary circuit; a comparator including a first input configured to receive a drain-to-source voltage of a field effect transistor; and a second input to receive the reference voltage; and a signal generator to deliver a driving signal to a gate terminal of the field effect transistor to drive the field effect transistor to an ON state after the drain-to-source voltage of the first low side field effect transistor becomes less than the reference voltage and to an OFF state after the drain-to-source voltage of the field effect transistor becomes greater than the reference voltage.

Methods and device to drive a transistor for synchronous rectification

A LED driving circuit includes a power factor correction circuit receiving a rectified mains voltage and providing output to a DC voltage bus, a string of LEDs connected in series, a voltage converter receiving input from the DC voltage bus and providing output to the string of LEDs, and a microcontroller. The microcontroller receives a plurality of digital feedback signals from the voltage converter, controls the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, and receive a plurality of feedback signals from the power factor correction circuit. Based on the plurality of feedback signals, the microcontroller operates the power factor correction circuit in transition mode where the user desired brightness level is above a threshold brightness, and operates the power factor correction circuit in discontinuous mode where the user desired brightness level is below the threshold brightness.

A power supply has a transformer with primary and secondary windings. A first terminal of the primary-winding is coupled to a power-input. A PFC includes a low-voltage circuit correcting power factor of the power signal, having a supply-input receiving a supply voltage during normal operation, a feedback-input coupled to a first terminal of the secondary-winding, and a gate-drive-output. A high-voltage startup circuit powers the low-voltage circuit during startup. Periphery circuitry includes a transient voltage suppression diode having an anode coupled to supply power to the high-voltage startup circuit and a cathode coupled to the power-input, a diode having an anode coupled to the first terminal of the secondary-winding and a cathode coupled to the supply-input of the low-voltage circuit. A capacitor is coupled between the supply-input and ground. A transistor has a drain coupled to a second terminal of the primary-winding and a gate coupled to the gate-drive-output.

Enhancing high-voltage startup voltage rating for PWM controllers with internal high voltage startup circuit

A Darlington switch in series with a biasing circuit is biased in an ON state by default to generate a supply voltage for a controller integrated circuit chip during start-up. On powering up, the supply voltage for the controller integrated circuit chip rises. When the supply voltage exceeds a minimum operating voltage threshold, the controller integrated circuit chip is enabled for operation and an auxiliary supply circuit begins generating the supply voltage for the controller integrated circuit chip. The Darlington switch is turned OFF when the supply voltage being generated by the auxiliary circuit is sufficiently higher than a threshold associated with the minimum operating voltage threshold. The circuit for controlling ON/OFF state of the Darlington switch has a substantially lower static power dissipation than the biasing circuit.

Scheme to reduce static power consumption in analog controller based power converters requiring an external high voltage startup circuit

Disclosed herein is a circuit including a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.

A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.

Driving circuit using buck converter capable of generating sufficient voltage to power a LED circuit and associated auxiliary circuitry in a normal mode of operation, and insufficient to power the LED circuit but sufficient to power the associated auxiliary circuitry in an off mode of operation

A circuit includes a voltage converter converting source voltage to supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between first and second node nodes. Feedback circuitry couples the second node to the feedback node when a voltage at the second node exceeds a first overvoltage, in a first mode of operation. The feedback circuitry couples the second node to the feedback node when the voltage at the second node exceeds a second overvoltage less than the first overvoltage, in a second mode of operation. Impedance circuitry is coupled between the first node and a third node and generates an auxiliary supply voltage and an auxiliary ground voltage when the circuit is in both the first and second modes, the auxiliary supply voltage being less than the supply voltage in both the first and second modes.

Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

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Nahan, India

Akshat Jain