Micron Technology Incorporated

Akram Ditali

Salman Akram

Tianhong Zhang

Charles H Dennison

Pierre C Fazan

Viju K Mathews

Roy Maddox

Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers

Semiconductor constructions

Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers

A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate. Transistors and transistor gates fabricated according to the above and other methods are disclosed. Further, a transistor includes a semiconductive material and a transistor gate having gate oxide positioned therebetween. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. First insulative spacers are formed proximate the gate edges, with the first insulative spacers being doped with at least one of chlorine or fluorine. Second insulative spacers formed over the first insulative spacers.

Semiconductor processing method and field effect transistor

Methods of forming a transistor gate

One aspect of the invention provides a transistor including semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween, and the gate oxide has opposing edges substantially laterally aligned with the opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. At least one of fluorine or chlorine is concentrated in the gate oxide layer between the semiconductive material and the transistor gate more proximate at least one of the gate edges than the central region. Another aspect of the invention provides a transistor comprising semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween, and the gate oxide has opposing edges substantially laterally aligned with the opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. At least one of fluorine or chlorine is concentrated in the gate oxide layer between the semiconductive material and the transistor gate more proximate at least one of the gate edges than the central region.

Field effect transistor having improved hot carrier immunity

A multiple implant lightly doped drain ('MILDD') field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Method of forming a multiple implant lightly doped drain (MILDD) field

Method of forming a multiple inplant lightly doped drain (MILDD) field

Multiple implant lightly doped drain (MILDD) field effect transistor

The present invention includes a method of forming semiconductor oxide layers and, in particular, gate oxide layers, in MOS semiconductor devices formed on silicon substrates. The method includes the steps of forming a first silicon oxide sublayer on the silicon substrate in an atmosphere including primarily oxygen, and forming a second silicon oxide sublayer over the first sublayer in an atmosphere including primarily nitrous oxide (N.sub.2 O). Preferably, the first and second sublayers represent 80 percent and 20 percent, respectively, of the silicon oxide layer.

Growing community of inventors

Boise, ID, United States of America

Akram Ditali