Texas Instruments Corporation

Advanced Micro Devices Corporation

Globalfoundries Inc.

George Mason University

Akram Ali Salman

Henry Litzmann Edwards

Farzan Farbiz

Aravind Chennimalai Appaswamy

Binghua Hu

Stephen G Beebe

Amitava Chatterjee

Xiaoju Wu

Gianluca Boselli

Md Iqbal Mahmud

Ann Margaret Concannon

Lili Yu

Zaichen Chen

Yang Xiu

Alexei Sadovnikov

Guruvayurappan Mathur

John Eric Kunz, Jr

Muhammad Yusuf Ali

Krishna Praveen Mysore Rajagopal

Umamaheswari Aghoram

Mariano Dissegna

Shuqing Cao

Ryo Tsukahara

Souvick Mitra

James Paul Di Sarro

Anand Seshadri

Kemal Tamer San

Jun Cai

Kurt Taylor

Michael Allen Ball

Sunil Kumar Dusa

Dimitris E Ioannou

Xuejun Zhao

An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.

Silicide-block-ring body layout for non-integrated body LDMOS and LDMOS-based lateral IGBT

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device

An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Isolation structure for IC with epi regions sharing the same tank

An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

eFUSE programming feedback circuits and methods

A semiconductor controlled rectifier (FIG.A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region () having a first conductivity type (N) and a first heavily doped region () having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region () having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region () having the first conductivity type is formed within the second lightly doped region. A buried layer () having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

ESD protection circuit with isolated SCR for negative voltage operation

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

ESD protection device with deep trench isolation islands

A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Positive strike SCR, negative strike SCR, and a bidirectional ESD structure that utilizes the positive strike SCR and the negative strike SCR

An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

Back ballasted vertical NPN transistor

An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.

A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

Zener-triggered transistor with vertically integrated Zener diode

An electrostatic discharge (ESD) protection circuit (FIG.A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL) having a second conductivity type is formed below a face of the substrate. A first terminal () and a second terminal () are formed at a face of the substrate. A first ESD protection device () has a first current path between the first terminal and the buried layer. A second ESD protection device () has a second current path in series with the first current path and between the second terminal and the buried layer.

Series connected ESD protection circuit

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Plano, TX, United States of America

Akram Ali Salman