Sony Computer Entertainment Inc.

Sony Interactive Entertainment Inc.

Sony Corporation

International Business Machines Corporation

Akiyuki Hatakeyama

Masakazu Suzuoki

Varun Bhadauria

Jeffrey Litz

Mark Evan Cerny

Masahiro Yasue

Simon Whittaker

Harm Peter Hofstee

Makoto Tanaka

Michael Norman Day

David Jones Craft

Maximino Aguilar, Jr

Atsushi Hayashi

Keiso Shimakawa

Yoichi Nishino

Tadayasu Hakamatani

Taichi Niki

Provided are an access control apparatus, an access control method, and a program that can reduce risks of tampering with a block while at the same time keeping ICV data size to a minimum. An individual key generation section () generates an individual key specific to an information processing apparatus (). An ICV data generation section () generates, by using an individual key, ICV data that is based on verified digest value data, specific to the information processing apparatus (), and smaller in data size than the digest value data. An ICV calculation section () calculates, by using the individual key, an ICV based on the block to which access is requested. A comparison section () compares the ICV indicated by a part of the ICV data corresponding to the block with the ICV calculated by the ICV calculation section (). A writing section () writes the block to a memory in a case where the comparison succeeds.

Access control apparatus, access control method, and program

A method, system and non-transitory computer readable instructions for application patching comprising, concatenating compressed data or uncompressed data or a mixture of compressed and uncompressed data into a continuous data set into a continuous data set and dividing the continuous data set into variable sized data chunks. Compressing each of the variable sized data chunks and dividing each of the variable sized data chunks into fixed size data blocks. Encrypting the fixed size data blocks to generate encrypted fixed size data blocks and storing the encrypted fixed sized data blocks or sending the encrypted fixed size data blocks over a network.

Application patching using variable-sized units

Provided are a digest value calculating device, an access device, a digest value calculating method, an access method, and a program that have a small possibility of collision between digest values even though a digest value calculation load is light. A parameter value determining section () determines a value of a common parameter used in common for each of a plurality of paths respectively associated with inodes. A digest value calculating section () calculates, for each of the plurality of paths, a digest value corresponding to the path on the basis of the value of the common parameter and a name of the path. A record generating section () associates the digest value corresponding to the path and an inode corresponding to the path with each other.

Digest value calculating device, access device, digest value calculating method, access method, and program

A method, system and non-transitory computer readable instructions for data change detection includes decrypting encrypted patch data that includes compressed variable sized patch data chunks. The compressed variable sized patch data chunks are decompressed and a strong hash value is generated. The strong hash values are compared with strong hash values of corresponding variable sized application data chunks to determine a potentially non-referable patch data chunk. A bloom filter is generated for the variable sized application data chunks. A rolling hash value for a window of the potentially non-referable patch data chunk is used to determine a potentially referable area from the potentially non-referable patch data chunk. The potentially referable area is designated as referable when a weak hash and a strong hash of an application data chunk matches the weak hash and the strong hash of the potentially referable area.

Data change detection using variable-sized data chunks

Disclosed herein is an information processing apparatus including a first holding section configured to hold a first patch file, a second holding section configured to hold a first hash value of each data block in a second patch file including a plurality of data blocks each having a predetermined block size, a hash value calculating section configured to calculate a first hash value of data corresponding to the block size in the first patch file, and a comparing section configured to compare the first hash value calculated by the hash value calculating section with the first hash value of each data block held in the second holding section, as a first-stage comparison process.

Information processing apparatus

A method, system and non-transitory computer readable instructions for application patching comprising, concatenating uncompressed data into a continuous data set and dividing the continuous data set into variable sized data chunks. Compressing each of the variable sized data chunks and dividing each of the variable sized data chunks into fixed size data blocks. Encrypting the fixed size data blocks to generate encrypted fixed size data blocks and sending the encrypted fixed size data blocks over a network.

An information processing device includes: an application recording portion in which application software is recorded; a patch obtaining portion obtaining patch data from a server; a patch recording portion in which the obtained patch data is recorded; and an application executing portion executing an application using the application software and the patch data. The patch obtaining portion includes a difference information obtaining unit obtaining data block difference information between a latest patch file retained by the server and a patch file recorded in the patch recording portion, and a download executing unit downloading an updated data block from the latest patch file according to the difference information.

Information processing device and difference generating for software patching system

A system and method is disclosed which may include providing at least one processor with an integrally disposed random number generator (RNG) therein; entering a protected mode by said at least one processor; and generating a random number using said RNG in said at least one processor after entering said protected mode.

Methods and apparatus for generating a random number in one or more isolated processors

A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

Methods and apparatus for dynamic prediction by software

A processor and associated local memory are capable of operative connection to a main memory such that data may be read from the main memory for use in the local memory, and the processor is operable to carry out actions, including: entering a secure mode of operation where externally initiated requests to read data from or write data into the processor are not serviced but internally initiated data transfers are serviced; reading a decryption program from a storage medium into the local memory of the processor; reading an encrypted authentication program into the local memory of the processor; decrypting the encrypted authentication program using a decryption program; and transitioning functionality of the processor from the decryption program to the authentication program.

Methods and apparatus for facilitating a secure processor functional transition

In a multi-processor system including a plurality of processors capable of being operatively coupled to the main memory and each processor including an associated local memory, and at least one main processor operable to control access by the processors to data within the main memory and within the processors, methods and apparatus provide for: entering a secure mode of operation within at least one of the processors in which no requests initiated by others of the processors for data transfers into or out of the at least one processor are serviced, but such transfers initiated by the at least one processor are serviced subject to the access controlled by the main processing unit; and using the main processing unit to exclude access to data associated with at least one further processor by others of the processors except for the at least one processor.

Methods and apparatus for secure processor collaboration in a multi-processor system

Methods and apparatus provide for: requiring that a content provider seeking to have its content executed by a processing system enter into an accord with a processing system provider; receiving a second key and a digital signature from the content provider to the processing system provider, the second key being operable to decrypt the content when it has been encrypted with a first key, and the digital signature indicating that the accord has been reached; receiving the encrypted content from the content provider in a memory of the processing system; and preventing use of one or more processing resources of the processing system that are otherwise operable to facilitate the execution of the content unless the digital signature is received from the processing system provider.

Methods and apparatus for content control using processor resource management

A system and method are disclosed which may include entering a secure mode by a processor, whereby the processor may initiate a transfer of information into or out of the processor, but no external device may initiate a transfer of information into or out of the processor; sending a DMA (direct memory access) command including at least one authorization code from the processor to at least one trusted data storage region external to the processor; evaluating the authorization code; and enabling the processor to access at least one trusted data storage location within the trusted data storage region if the authorization code is valid.

Methods and apparatus for accessing resources using a multiprocessor in a trusted mode

Methods and apparatus provide for placing an apparatus into at least one of a plurality of operational modes, wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the local memory over the bus.

Methods and apparatus for secure data processing and transmission

Methods and apparatus provide for: entering a secure mode in which a given processor may initiate a transfer of information into or out of said processor, but no external device may initiate a transfer of information into or out of said processor; and programming at least one trusted data storage location using a direct memory access (DMA) command to be one of read-only, write-only, readable and writeable, limited access, and reset, where said at least one trusted data storage location is located external to said processor.

Growing community of inventors

Kanagawa, Japan

Akiyuki Hatakeyama