Fujitsu Corporation

Fujitsu Semiconductor Limited

Akiyoshi Watanabe

Makoto Yasuda

Yoshihiro Matsuoka

Osamu Kobayashi

The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.

Capacitor and method for fabricating the same, and semiconductor device and method for fabricating the same

The semiconductor device comprises a device isolation regionformed in a semiconductor substratea lower electrodeformed in a device regiondefined by the device isolation region and formed of an impurity diffused layer, a dielectric filmof a thermal oxide film formed on the lower electrode, an upper electrodeformed on the dielectric film, an insulation layerformed on the semiconductor substrate, covering the upper electrode, a first conductor plugburied in a first contact holeformed down to the lower electrode, and a second conductor plugburied in a second contact holeformed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrodeis not formed in the device isolation regionwhereby the short-circuit between the upper electrodeand the lower electrodein the cavity can be prevented. Thus, a capacitor of high reliability can be provided.

Capacitor having upper electrode not formed over device isolation region

A lower electrode of a capacitor element and a wiring are formed in a wiring layer that is one layer below an uppermost wiring layer. Subsequently, after the formation of a capacitance insulating film, a TiN film is formed on the entire surface thereof, and then the TiN film is patterned, thereby forming an upper electrode of a capacitor element and a lead wiring for electrically connecting the upper electrode to a wiring of a third wiring layer. Furthermore, in the uppermost layer, a shield is formed covering the upper portion of the capacitor element.

Semiconductor device and method of manufacturing the same

A silicon film is formed on a semiconductor substrate, and a silicon oxide film and a polycrystalline silicon film are formed thereon. Patterning is performed for the polycrystalline silicon film to form a capacitive upper electrode. Then, patterning is performed for the silicon oxide film to form a capacitive dielectric film below the capacitive upper electrode, the capacitive dielectric film having a shape larger than that of the capacitive upper electrode. Subsequently, an anti-reflection coating film (silicon nitride film which is silicon-rich) is formed on a full surface. Then, patterning is performed for the silicon film by means of photolithography to form a capacitive lower electrode and a gate electrode of a transistor.

Method of forming semiconductor device including patterning lower electrode of capacitor and gate electrode of transistor with same resist

A gate insulating film is formed on the surface of active regions of a semiconductor substrate, and a first polysilicon film is deposited on the semiconductor substrate. Impurities are selectively doped into the first silicon film in an area where a capacitor is to be formed. A dielectric film is formed on the first silicon film. A second silicon film doped with impurities is formed on the dielectric film. The second silicon film and dielectric film are patterned so that the second silicon film and dielectric film are left in the area where the capacitor is to be formed, and not left in the area where MISFET are to be formed. A third silicon film is deposited on the whole surface of the substrate. A mask pattern covers the surface of the third silicon film in the area included by the patterned second silicon film as viewed along a direction normal to the substrate surface and in the area where a gate electrode of MISFET is to be formed, and the silicon films are selectively etched under the conditions that the dielectric film is not etched. A semiconductor device can be formed which has a low voltage dependency of a capacitor electrostatic capacitance and a small variation of electrostatic capacitances.

Semiconductor device manufacture method and semiconductor device comprising capacitor and MISFET

A first silicon film is deposited on a semiconductor substrate. A capacitor dielectric film is deposited on the first silicon film. A second silicon film is deposited on the capacitor dielectric film. The second silicon film is patterned to leave an upper electrode made of the second silicon film above an insulating surface of the semiconductor substrate. A first insulating film is deposited on the upper electrode and the capacitor dielectric film. A lamination structure of the first insulating film and the capacitor dielectric film is anisotropically etched to leave a spacer insulating film made of the first insulating film on the side walls of the upper electrode and to leave a portion of the capacitor dielectric film under the upper electrode and the spacer insulating film. The first silicon film is patterned to leave a lower electrode made of the first silicon film in an area inclusive of the upper electrode and the spacer insulating film.

Growing community of inventors

Kawasaki, Japan

Akiyoshi Watanabe