Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Akiyoshi Tamura

Keiichi Murayama

Masanobu Nogome

Kenichi Miyajima

Yoshiaki Kato

Yoshiharu Anda

Tomoya Uda

Hirotaka Miyamoto

Kazushi Nakazawa

Kazutsune Miyanaga

Yoshitaka Kuroishi

Manabu Yanagihara

Masatoshi Kitagawa

Takahiro Yokoyama

Tadayoshi Nakatsuka

Yorito Ota

Katsunori Nishii

Yoshito Ikeda

Mitsuru Nishitsuji

Toshiharu Tambo

Keisuke Kojima

Takeshi Onuma

Takahiro Kitazawa

Katsuyoshi Tara

Tuneo Yamaguchi

A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Semiconductor device

A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.

The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof

The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer.

Heterojunction bipolar transistor and manufacturing method thereof

A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.

Semiconductor device and manufacturing method of the same

The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate; an n-type GaAs sub-collector layer; an n-type GaAs collector layer; a p-type GaAs base layer; an emitter layer; an n-type GaAs emitter cap layer; and an n-type InGaAs emitter contact layerThe emitter layerhas a multilayer structure including an n-type or non-doped first emitter layerand an n-type second emitter layerwhich are laminated in sequence. The first emitter layeris made of a semiconductor material including Al, while the second emitter layeris made of InGa1-xP (0&#x3c;x&#x3c;1).

Heterojunction bipolar transistor having an emitter layer made of a semiconductor material including aluminum

It is the object of the present invention to provide a manufacturing method for a compound semiconductor device capable of removing remaining organic substances without deteriorating a characteristic of the compound semiconductor device, wherein a surface of an i-type AlGaAs schottky layer is cleaned in a state where light is blocked using either one of ozonized (O) water whose ozone concentration is at most 13 mg/L and hydrogenated (H) water whose hydrogen ion concentration (pH) is from 6 to 8 inclusive, or using both of the ozonized water and the hydrogenated water after a schottky electrode made of Ti/Al/Ti is evaporated onto the exposed i-type AlGaAs schottky layer and a lift-off operation is performed using a remover.

Manufacturing method for compound semiconductor device

A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layerthat is made of GaAs; an n-type first collectorthat is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collectorand is formed on the sub-collector layer; a second collector layerthat is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layerand is formed on the first collector layer; a p-type base layerthat is made of GaAs and is formed on the second collector layer; and emitter layerthat is made of a semiconductor material with a larger band gap than that of the base layerand is formed on the base layer

Hetero-junction bipolar transistor and manufacturing method thereof

A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate, a GaAs buffer layerthat is formed on the semi-insulating GaAs substrate, AlGaAs buffer layer, a channel layer, a spacer layer, a carrier supply layer, a spacer layer, a Schottky layercomposed of an undoped InGaP material, and an n-type GaAs cap layerA gate electrodeis formed on the Schottky layer, and is composed of LaBand has a Schottky contact with the Schottky layer, and ohmic electrodesare formed on the n-type GaAs cap layer

Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof

A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs () having a gate electrode with a gate length of not more than 0.8 &#x3bc;m are formed on a semiconductor substrate in which a buffer layer () having an impurity concentration of at least 10cmand at most 10cmis formed on a semi-insulating semiconductor () having at least 10cmand at most 10cmp-type or n-type impurities and an active layer () having a p-type or n-type impurity concentration of at least 10cmand at most 10cmis formed on the buffer layer. N FETs are combined with each other, and when 1&#x2266;m&#x2266;n&#x2212;1 (n and m are integers, n&#x3e;1), a drain terminal of an m-th FET is connected to a source terminal of an (m+1)th FET, resistors () are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.

A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.

Semiconductor device including a photosensitive resin covering at least a portion of a substrate having a via hole

The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.

Heterojunction bipolar transistor and method for fabricating the same

A GaAs substrateis rotated, a photosensitive silicone resistis applied on a surface of the GaAs substrateon which an aperture of a holeto be a via hole, and an inside of the holeto be the via hole is filled in with the photosensitive silicone resistNext, the GaAs substrateis further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resiston the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the holeto be the via hole penetrates the GaAs substratefrom the surface to the reverse side and the via holeis formed. Next, a reverse side electrodeis formed on the reverse side of the GaAs substrateNext, the GaAs sustrateis divided chip by chip and chips are laid on a substrate for assemblyvia an adhesive metal

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Suita, Japan

Akiyoshi Tamura