Elpida Memory, Inc.

Sharp Kabushiki Kaisha Corporation

Dainichi Printing Co., Ltd.

Akiyoshi Seko

Isamu Asano

Kazuya Ishihara

Natsuki Sato

Takashi Nakano

Nobuyoshi Awaya

Tatsuya Matano

Yukio Tamai

Yukio Fuji

Mitsuru Nakura

A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element.

Semiconductor memory device and semiconductor device

A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells.

Semiconductor memory device

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, first and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element.

Semiconductor device

A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.

Control method of non-volatile semiconductor device

A nonvolatile memory device () is provided with a semiconductor substrate, a plurality of active regions () formed on the semiconductor substrate and extending in a band, a plurality of select active elements () formed in the active regions () and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes () electrically connected to the first impurity diffusion region, a variable resistance layer () electrically connected to the first electrodes (), and a plurality of second electrodes electrically connected to the variable resistance layer (). Among the plurality of first electrodes () and the plurality of second electrodes, an array direction of at least one pair of the first electrodes () and the second electrodes that are electrically connected to the same variable resistance layer (), and a direction of extension of the activation regions () are not parallel.

Nonvolatile memory device

An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Method of producing phase change memory device

A file wrapper for wrapping is provided. The file wrapper for wrapping comprises a file wrapper for wrapping comprising: a the cutting body, which comprises a unit piece of a covering paper and a backing paper of integral constitution that is bent to form a bag shape, sealing pieces provided to the covering paper and the backing paper, at the opening portion of the bag shape for inserting commodities, respectively, and side sticking pieces provided to the both sides portion of the covering paper. The one sealing piece is provided with a stopper of commodities after inserting them, and the other sealing piece is provided with the connecting piece inserted in the notch hole of the stopper and engaged thereto.

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Tokyo, Japan

Akiyoshi Seko