Hitachi, Ltd.

Akiyoshi Osumi

Takashi Hotta

Shigeya Tanaka

Kotaro Shimamura

Hideo Sawamoto

Toshihiko Kurihara

Koji Saito

Masahiro Iwamura

Fumio Murabayashi

A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Data processor having cache memory

Data processor with variable types of cache memories and a controller for selecting a cache memory to be access

Data processor with variable types of cache memories

A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal. As to the second MOS transistors, one is connected in parallel to the second impedance element and each of the remaining ones is connected between a common connection of a respective pair of adjacent ones of the series-connected first MOS transistors and the second power supply terminal. There is thus effected a speed-up of the carry signal and thereby a speeding-up of the signal processing. There is also provided a wiring scheme for preventing noise interference between different wirings. Moreover, a device has been schemed for a plurality of logic circuit blocks and including a data signal path for interconnecting different logic circuit blocks and facilitating the interfacing of a current-driven signal.

Carry propagating device

A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor. The arrangement results in reducing a signal amplitude on the signal bus, thereby speeding up the transmission of the data signal and reducing noise of the signal.

Current-driven signal interface implemented in semiconductor integrated

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Hitachi, Japan

Akiyoshi Osumi