Sharp Kabushiki Kaisha Corporation

Akitsu Ayukawa

Shigeo Onishi

Kenichi Tanaka

Hiroshi Ishihara

Yoshimitsu Yamauchi

Keizo Sakiyama

The disclosed invention is a process for fabricating a semiconductor device comprising the steps of:

Process for producing semiconductor device comprising two step annealing

A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.

Process for fabricating nonvolatile random access memory having a tunnel

A process for manufacturing a semiconductor device, including the steps of: forming a oxide film over the entire surface of a semiconductor substrate formed with a gate electrode having side walls on opposite sides thereof with intervention of a gate oxide film, followed by implanting an impurity into a predetermined region; subjecting the substrate to a first heat treatment; removing the oxide film existing in the predetermined region; and subjecting the substrate to a second heat treatment in an ammonia or oxygen gas atmosphere.

Process for manufacturing a semiconductor device including heat

A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portion as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the surface.

Method for manufacturing a semiconductor device

A process for producing a semiconductor device comprising the steps of:

Process for producing semiconductor device

A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portions as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the surface.

A method for fabricating a semiconductor device in which diffusion regions are formed in a silicon substrate with use of a gate electrode parts having side walls as a mask, including the steps of: (a) forming a gate electrode on a silicon substrate with a gate oxide interposed therebetween; (b) depositing an insulation film to entirely cover the substrate and the gate electrode, followed by depositing a polysilicon or amorphous silicon layer on the insulation film; (c) forming side walls of SiO.sub.2 on lateral sides of the gate electrode covered with the insulation film and the polysilicon or amorphous silicon layer, followed by ion implantation; and (d) subjecting the resulting substrate to a heat treatment at a medium temperature after removal of the side walls, followed by stacking an interlayer insulator after removal of the polysilicon or amorphous silicon layer, and subjecting the resultant to a heat treatment at a high temperature.

Growing community of inventors

Tenri, Japan

Akitsu Ayukawa