Fujitsu Corporation

Akitoshi Ino

Tsutomu Tanaka

Hideki Sakata

Takao Kato

Haruhiko Ueno

Atsuhiro Suga

Yoshihiro Kusano

A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction. However, when the read instruction contends with the store instruction and a state transition signal, such as an instruction cancellation signal generated from an instruction controlling device, is detected, the cache write buffer controlling device changes the output signal to a storage request high signal that causes the storage operation to have precedence over the read operation.

Data processing apparatus with a cache controlling device

A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register. When the virtual address coincides with the other virtual address in the comparison circuit, the table entry converted by the update unit is written into an address of the main memory held in the third register.

Dynamic address translation allowing quick update of the change bit

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Kawasaki, Japan

Akitoshi Ino