Hitachi, Ltd.

Akishige Nakajima

Eiichi Hase

Masao Yamane

Tomoyoshi Mishima

Chushiro Kusano

Mitsuhiro Mori

Makoto Kudo

Takuma Tanimoto

Tooru Fujioka

Satoshi Tanaka

A microwave multi-stage power amplifier has matching circuits for input and output stages and one or more inter-stage matching circuits. The amplifier and a signal output pad and first and second voltage supply pads are formed at one and the same semi-insulating substrate. A first FET in the output stage has its drain connected to the first voltage supply pad through a first distributed line and further connected to the signal output pad through a second distributed line in which the first and second distributed lines contribute to formation of the matching circuit for the output stage. A second FET in a stage preceding to the output stage has its drain connected to the second voltage supply pad through a third distributed line serving as a connection conductor. The first distributed line has a width larger than that of the third distributed line and has a length which limits an impedance seen at the drain of the output stage FET towards the first voltage supply pad at an operation frequency of the amplifier to a value other than infinity.

Monolithic integrated circuit device having microwave power amplifier

In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.

Semiconductor device with reduced tunnel resistance and circuitry using

An electronic circuit is provided with a first field effect transistor and a second field effect transistor, in which a drain of the first field effect transistor connected to a source of the second field effect transistor. This electronic circuit inputs a first signal to a gate electrode of the first field effect transistor, inputs a second signal to a gate electrode of the second field effect transistor and outputs a signal from a drain of the second field effect transistor. This electronic circuit is a cascode circuit related to the current drivability of the second field effect transistor is set to be larger than the current drivability of the first field effect transistor, and there is an effect that third-order or higher order distortion characteristics of a cascode type or dual-gate circuit can be reduced.

Low-distortion cascode circuit

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Kokubunji, Japan

Akishige Nakajima