Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Akira Yamaoka

Kenichi Wada

Kazunori Kuriyama

Yooichi Shintani

Tsuguo Shimizu

Kiyoshi Inoue

Kiyoshi Ogawa

Hidenori Umeno

Eiki Kamada

Shunji Tanaka

Tohru Shonai

Katsumi Takeda

Masatoshi Haraguchi

Kazuhiko Matsumoto

Hiromichi Kainoh

Hiroo Watai

Hiromoto Sakaki

Tohru Hiraoka

Yoichi Shintani

Keiji Saijo

A logic circuit generating method and apparatus generating logic circuits of a circuit system by minimizing the fan-out count of cells or cell macros constituting information specific to the circuit system. According to the method, a Boolean expression and the polarities of its input/output variables are input from a design master file of the apparatus. The Boolean expression is then transformed into a two-branch tree composed of nodes represented by the logical operators of that expression. In the two-branch tree, the nodes representing a parent and a child logical operator are converted into a single node, whereby a multiple-branch tree is generated. That is, a plurality of gates are connected to a single net, or signal line. A cell library is referenced so that cells are assigned initially to the multiple-branch tree thus obtained. The initial cell assignment is performed preferentially starting from the cell whose fan-out count is the largest. This is done to minimize the number of loads represented by the assigned cells (i.e., the number of cells connected to the output net). The number of gate stages is then evaluated. The stage count is minimized by reassigning the cells. Finally, the acquired gate logic is output to the design master file.

Logic circuit generating method and apparatus

Under such a condition between outputs of AND circuits for outputting All '0' when one of zero detecting circuits of two register identifiers within an instruction register detects '0', instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

Logical-to-real address translation based on selective use of first and

Virtual machine system having an extended storage

In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having '1' set in the bit position corresponding to the receive program. On the basis of the above described bit position, the receive OS specifies a receive program and informs the receive program of that fact. The receive program reads a message from the communication buffer. Communication between the send program and the receive program is thus realized. A send instruction and a receive instruction respectively for exclusive use of sending and reading out a communication ID are prepared beforehand.

Multiprocessors including means for communicating with each other

A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at least each of the processors and the main storage. A shared storage apparatus is shared between the sub-systems to store exclusive control information, information on the processor-to-processor communications and an instruction to be transferred between the main storages and the shared storage apparatus when the information is accessed by each sub-system. The instruction designates a main storage address, a transfer data length and specified information on accessing the location of the shared storage apparatus and is decoded by the processors to that the main storage address is transferred to the main storage, whereas the specified information such as a data identifier and a relative address is transferred to the shared storage apparatus.

Multiprocessor system having subsystems which are loosely coupled

An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.

Instruction processor for processing branch instruction at high speed

Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.

Pipelined instruction processor capable of reading dependent operands in

A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.

Pipelined parallel data processing apparatus for directly transferring

A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

Pipelined data processor capable of decoding and executing plural

An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.

Information processing apparatus

A decimal multiplier device including a register A storing the multiplier, a register B storing the multiplicand, a shifter for outputting the output of the register A as it is or after having been shifted, based on a first signal, a gate for outputting the output of the register B or '0', based on a second signal, an adder/subtractor for adding the output of the shifter and that of the gate and storing the result thus obtained in the register A, and a decoder for receiving the value of a selected digit of the content of the register A and controlling the gate and the shifter by generating the first signal and the second signal based on the received value so that the multiplicand B is added n times, n corresponding to the received value, to the content of the register A or substracted (10-n) times therefrom. The register A, the shifter and the adder/subtractor form a single loop. Decimal multiplication is performed by controlling the shifter, when signals pass through the loop repeatedly.

Decimal multiplier device and method therefor

A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

Data processing system

This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division. A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively. The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

Coded decimal non-restoring divider

In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

Buffer storage including a swapping circuit

A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.

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Hadano, Japan

Akira Yamaoka