Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Video and Information System, Inc.

Akira Uragami

Ryutaro Horita

Toshiaki Matsubara

Yukio Suzuki

Shinichi Kojima

Masahiro Iwamura

Ikuro Masuda

Kenichi Hase

Shinji Kadono

Akihiko Hirano

Masayoshi Yoshimura

Syoichi Miyazawa

Manabu Shibata

Yasunaga Suzuki

Shoichi Miyazawa

Hiroshi Kimura

Yoji Nishio

Terumi Takashi

Fumio Murabayashi

Tsuguyoshi Hirooka

Shoichi Kotoku

Fumiaki Matsuzaki

Yoshitatsu Kojima

Tatsumi Yamauchi

Takashi Watanabe

Eisaku Saiki

Takashi Nara

Shintaro Suzumura

Shyoichi Miyazawa

Fukashi Ohi

Masaou Takahashi

Yoshinori Yoshino

Haruo Mamyoda

Tsuyoshi Tateyama

Yasuhiro Kanzawa

A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.

Magnetic disk storage apparatus

A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

Magnetic disk storage apparatus with phase sync circuit having

The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using it. The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts the operation state of the AD converter into the low power consumption state.

AD converter and magnetic recording/regenerating apparatus using thereof

A semiconductor device (CPLT) of the invention comprises a first terminal (R) to which analog data is to be supplied, a digital/analog converter (DAC1) with its output coupled to the first terminal, a second terminal (R'0) to which digital data is to be supplied, a digital output circuit (DOB) with its output coupled to the second terminal, and a preparation circuit (PLM, SEL) which is coupled to respective inputs of the digital/analog converter and the digital output circuit. The preparation circuit prepares digital data to be processed (RR) for any one of input of the digital/analog converter and input of the digital output circuit.

One-chip semiconductor integrated circuit device capable of outputting

The present invention provides an AD converter which operates at high speed with low power consumption and a magnetic recording/regenerating apparatus using the same. The magnetic recording/regenerating apparatus has a current controller for switching the operating current of the comparator of the AD converter and an ADC controller for receiving an instruction of the conversion speed corresponding to the regenerating frequency. When the current controller receives an instruction for decreasing the conversion speed, it puts an operation state of the AD converter into a low power consumption state.

Ad converter and magnetic recording/regenerating apparatus using the same

A semiconductor device (CPLT) of the invention comprises a first terminal (R) to which analog data is to be supplied, a digital/analog converter (DAC1) with its output coupled to the first terminal, a second terminal (R'0) to which digital data is to be supplied, a digital output circuit (DOB) with its output coupled to the second terminal, and a preparation means (PLM, SEL) which is coupled to respective inputs of the digital/analog converter and the digital output circuit, and prepares digital data to be processed (RR) for any one of input of the digital/analog converter and input of the digital output circuit.

In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

BiCMOS tri-state output driver

A data device for introducing the data read from a recording medium includes first creation device for receiving a read code signal corresponding to the data stored on a data recording medium to create first two phase signals which repeat inversion with a substantially equal period to each other on the basis of a change in the waveform of the read code; second creation device for receiving the first two phase signals to create second two phase signals with their one phase occupying most of their period having an overlapping portion with each other, the period being twice as long as that of the first two phase signals; and third creation device for receiving the read code signal and said second two phase signals to create a second code signal corresponding to the read code signal which shifts during the one phase period of said second two phase signals. The second two phase signals serve to extend sufficiently the window for introducing the read code to provide stabilized read for the data including jitter due to rotation fluctuation of the recording medium.

Sync data introduction method and system

A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.

Magnetic disk system and waveform equalizer therefor

The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.

Semiconductor integrated circuit device including high-speed operating

A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Semiconductor integrated circuit device with built-in memory circuit

In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Level conversion circuitry for a semiconductor integrated circuit

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Takasaki, Japan

Akira Uragami