Olympus Corporation

Ricoh Company, Ltd.

Kaken Chemical Co., Ltd.

Agc Inc.

Olympus Corportion

Akira Ueno

Yoshinobu Tanaka

Keisuke Nakazono

Takashi Yanada

Ryusuke Tsuchida

Tomoyuki Sengoku

Masami Shimamura

Hideru Ikeda

Yutaka Murata

Ayahiko Takahashi

Atsushi Ishihara

Akira Takahashi

Toshiyuki Yamamoto

Hideaki Furukawa

Yasuhiko Hamazaki

Tomonori Yonemoto

Shozo Kawabata

Kazue Chida

Yasuo Shiraishi

Tomomi Sekimoto

Hironobu Tomita

Hiroshi Takeda

Tetsuya Toyoda

Masaomi Tomizawa

Kenji Koyama

Motoo Azuma

Masaki Higurashi

Saburo Sasaki

Susumu Iguchi

Dai Kawase

Keiji Himuro

Shinsuke Homma

Yoshio Serikawa

Hiroshi Terui

Mikio Kobayashi

Tokio Ishino

Takenori Miura

Naoto Funakoshi

Yoshihiko Shimura

Shigeru Mitsu

Yukihisa Narazaki

Katsumas Saga

Koji Amemiya

Toru Sakaguchi

Touru Sakaguchi

Nobuyuki Ban

Haruo Yonemori

Hideaki Fukukawa

An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Image processing device

The present invention relates to a float-glass manufacturing apparatus including a float bath and a heat treatment furnace, in which the heat treatment furnace includes: a dross box including a plurality of lift-out rolls; an annealing furnace including a plurality of lehr rolls; a first partitioning part; a second partitioning part; a gas ejection nozzle; and a guide member.

Float glass production device and float glass production method

An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.

Image processing device and imaging device

A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Memory access device, image processing device and imaging device

A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

Semiconductor integrated circuit

An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

Data transfer device, image processing device, and imaging device

Motion vector calculator sets motion vector of block corresponding to partial area of first image based on the block and similarity between the block and partial area of second image, motion vector reliability calculator calculates reliability of the motion vector based on distribution of the similarities, motion vector corrector corrects motion vector of low-reliability block having reliability lower than predetermined reliability based on motion vector of high-reliability block different from the low-reliability block and having reliability equal to or higher than the predetermined reliability, and image processor sets second pixel of the second image and corresponds to first pixel of the first image based on the motion vector corrected by the motion vector corrector, and performs image processing using signal value of the first pixel and signal value of the second pixel.

Image processing device, image processing method, and computer program product for correcting a motion vector of a low-reliability block

A data transfer device including a buffer unit configured to temporarily store transfer data that is transferred to a common bus, a write control unit configured to write input data as the transfer data to the buffer unit, a read control unit configured to read the transfer data from the buffer unit, an interface unit configured to transfer the transfer data to the common bus according to a predetermined bus protocol, the transfer data being read from the buffer unit by the read control unit, and a band-smoothing unit configured to smooth a band of the common bus by switching between the time intervals between pieces of the transfer data based on a position of the transfer data in a frame image, during a period when the transfer data is transferred to the common bus based on a position of the transfer data in a frame image.

Data transfer device and data transfer method having a shorter time interval between pieces of final transfer data in a frame image

There is provided an image processing device includes an image processing section including a pipeline in which a plurality of processing modules is connected in series, and a system control section performing setting the pipeline processing to be performed by the image processing section. Each of the processing modules includes a data buffer temporarily store the data, on arithmetic section configured to perform an arithmetic operation of the process according to a setting of processing content by the system control section, and a control section configured to select a data transfer path within the processing module and control an operation of the data buffer according to a setting of a data transfer path by the system control section. The image processing section further includes a connection switching section configured to switch a connection between the processing modules according to a setting of a pipeline configuration by the system control section.

Image processing device and image processing method

A data transfer device includes a buffer unit temporarily storing transfer data to be transferred to a common bus, a write control unit writing input data as the transfer data to the buffer unit and outputs a notification signal, a read control unit reading the transfer data from the buffer unit, an interface unit transferring the transfer data to the common bus according to a predetermined bus protocol, and a band-smoothing unit which smoothes a band of the common bus by delaying the notification signal, generating a read control signal, and outputting the read control signal to the read control unit, wherein when previous transfer data which has been read from the buffer unit already exists and a DMA transfer receipt ACK responding to a DMA transfer request REQ is received by the interface unit, the read control unit reads current transfer data from the buffer unit.

Data transfer device and data transfer method for smoothing data to a common bus

There is provided an image processing device include an image processing section including a pipeline in which a plurality of processing modules is connected in series, each processing modules being configured to perform a predetermined process on input data, and the image processing section performing pipeline processing by the processing modules sequentially performing the process. Each of the processing modules includes a data buffer configured to temporarily store the data in unit of processing, and a control section configured to determine whether or not to store the data in the data buffer on the basis of a state of a data flow in the pipeline processing and a state of the data stored in the data buffer, and to select a path within the processing module by which the data is transferred on the basis of a determination result, and to control an operation of the data buffer.

A solid-state imaging device includes a pixel signal-processing unit which includes a plurality of pixels arranged in a two-dimensional matrix, wherein the pixel signal-processing unit outputs an total pixel signal while outputting a reduced pixel signal; a difference calculation unit which outputs a digital value obtained by calculating a difference between a digital value indicating a magnitude of the total pixel signal and a digital value indicating a magnitude of the reduced pixel signal; and a bit number reduction unit which reduces the number of bits of either the digital value obtained by calculating the difference, or the digital value indicating the magnitude of the total pixel signal, and outputs a digital value whose number of bits is reduced, wherein the solid-state imaging device outputs the digital value corresponding to the total pixel signal and the digital value indicating the magnitude of the reduced pixel signal.

Solid-state imaging device and imaging system

A solid-state imaging device includes a pixel signal processing unit which has a plurality of pixels disposed in a two-dimensional matrix, outputs each of pixel signals generated by all pixels as a total pixel signal, and outputs each of the pixel signals generated by the pixels with the number of pixels reduced to a prescribed number of pixels as a reduced pixel signal, a bit reduction method determination unit which determines a bit reduction method for reducing the number of pixels of a digital value representing the amount of the total pixel signal based on the reduced pixel signal, and a bit reduction unit which reduces the number of bits of the digital value based on the bit reduction method and outputs the digital value with the reduced number of bits as a digital value corresponding to the total pixel signal.

Solid-state imaging device and imaging system using a bit reduction method based on a reduced pixel signal

A calculation device includes a plurality of calculation processing units configured to perform different processes with each other, a plurality of calculators configured to perform a same calculation, and a control unit configured to control a number of the calculators to be operated during each of a plurality of divided periods based on a length of a predetermined processing period and a number of calculations to be performed, such that a number of data which is equal to a number of calculations is processed within a predetermined processing period, and that the number of the calculators to be operated during each of the plurality of divided periods is averaged, the divided periods being obtained by dividing up the predetermined processing period.

Calculation device

Growing community of inventors

Tokyo, Japan

Akira Ueno