Sanyo Electric Co., Ltd.

Akira Uemoto

Toshio Kakiuchi

Ryoichi Ando

Takao Myono

A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N-type wells formed in a surface of the P-type silicon substrate and separated from each other, a P-type well formed in the first deep N-type well, a shallow N-type well formed in the second deep N-type well, an N-channel type MOS transistor formed on a surface of the P-type well and a P-channel type MOS transistor formed on a surface of the shallow N-type well.

Semiconductor device

This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type second MOS transistor serving as protection transistors are connected in series between an output terminal and a ground potential. On the other hand, a P-channel type third MOS transistor and a P-channel type fourth MOS transistor serving as protection transistors are connected in series between a high power supply potential and the output terminal. These first, second, third, and fourth MOS transistors are formed of low withstand voltage MOS transistors.

Electrostatic damage protection device with protection transistor

P type well regions and are formed in N type well regions and respectively. The N type well regions and are formed separately each other. Charge transfer MOS transistors M and M are formed in the P type well regions and respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Growing community of inventors

Gunma, Japan

Akira Uemoto