Kabushiki Kaisha Toshiba

The University of Tokyo

Akira Toriumi

Akiko Ohata

Tomoharu Tanaka

Toru Tanzawa

Hiroshi Watanabe

Naoki Yasuda

Hideki Satake

Ken Uchida

Junji Koga

Yuichiro Mitani

Mizuki Ono

Koji Kita

Kazuya Ohuchi

Ryuji Ohba

Naoyuki Shigyo

Hiroyoshi Tanimoto

Hitoshi Higurashi

Makoto Yoshimi

Kiyoshi Kawamura

Tetsunori Wada

Yoshiki Yamamoto

Alfred Hubler

Fumiko Yamaguchi

Kazuyuki Tomida

A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVA) semiconductor board and a first oxide layer. The first oxide layer is composed of MOexisting on the board, where M is a first metal species selected from the group 4 (IVB); and M'O, where M&#x2032; is a second metal species selected from the group 3 (IIIB) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.

Semiconductor device and method for manufacturing the same

A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or &ldquo;thinned&rdquo; at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or &ldquo;polysilicon&rdquo; film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.

Semiconductor device with negative differential resistance characteristics

A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type diffusion layer region is formed in a surface layer of a p-type silicon substrate. A columnar structure portion is formed in which an n-type silicon layer, a buried insulation film and an n-type silicon layer are stacked over the n-type diffusion layer region and the buried insulation film is set back inward from both silicon layers. A silicon layer is formed over the side surface of the columnar structure portion, and a gate electrode is formed over the surface of the silicon layer with a gate insulation film that is interposed therebetween.

MOS transistor with vertical columnar structure

A new switching element and a circuit device and the like using the same element are provided, which comprises semiconductor in which a channel region is formed at an interface with an insulating film, first and second terminals S, D, which are located in corresponding manner to both ends of the channel region, and through which a tunnel current is let to flow into the channel region, and a third terminal G giving a high frequency vibration to a potential barrier of the channel region through the insulating film, wherein the tunnel current flowing into the channel region is increased as a value of an exponential function is increased with a predetermined threshold vibration frequency as a boundary value.

Quantum tunneling effect device and semiconductor composite substrate

In the manufacturing process of a field effect transistor, the main surface of the semiconductor layer is exposed to the atmosphere containing oxygen atoms and nitrogen atoms at first. Then, the gate insulating film is formed by introducing heavy hydrogen atoms therein such that the concentration of heavy hydrogen atoms in the interface of a gate insulating film and the gate electrode is higher than that of a middle portion of the gate insulating film located in the middle of the gate insulating film in the direction of the thickness of the gate insulating film. Subsequently, the gate electrode is formed on the gate insulating film. Then, source and drain regions are formed on the main surface of the semiconductor layer to sandwich the gate electrode therebetween. By virtue of the above-mentioned method, a gate insulating film having a small thickness and high electric stability can be obtained.

Field effect transistor and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and an electrode formed on the first insulating film. The first insulating film contains a halogen element and a combination of silicon and nitrogen or a combination of silicon, oxygen, and nitrogen. The maximum concentration of the halogen element in the first insulating film ranges from 10,atoms/cm,to 10,atoms/cm,inclusive. With this structure, the dielectric breakdown strength and the like of the insulating film increase, and the reliability of the insulating film improves.

Apparatus and method of improving an insulating film on a semiconductor device

A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.

Semiconductor integrated circuit device using a silicon-on-insulator

A semiconductor integrated circuit comprising a first functional block consisting essentially of a first circuit which includes a small junction device, and a second functional block consisting essentially of a second circuit which includes a field effect transistor, the second functional block being mutually connected to the first functional block.

Semiconductor device

Semiconductor integrated circuit having plural functional blocks,

According to the present invention, there is provided a correlation tunnel device capable of achieving a low power consumption without decreasing a drive force when a large-scale-integrated circuit is constituted. A correlation tunnel device according to the present invention comprises a first quantum dot structure including a first carrier confinement region having at least two discrete energy levels, a carrier conduction region adjacent to the first carrier confinement region, and a tunnel barrier arranged only between the first carrier confinement region and the conduction region, and a second quantum dot structure including a second carrier confinement region having at least two discrete energy levels, a carrier conduction region adjacent to the second carrier confinement region, and a tunnel barrier arranged only between the second carrier confinement region and the conduction region, wherein an energy level occupied by the carrier in the first carrier confinement region and an energy level occupied by the carrier in the second carrier confinement region have a correlation.

Correlation tunnel device

A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor. Alternatively, the present invention can be realized with three transistors where the memory cell includes: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.

Growing community of inventors

Yokohama, Japan

Akira Toriumi