Kabushiki Kaisha Toshiba

Akira Takiba

Masanori Kinugasa

Masaru Mizuta

Toru Fujii

Hiroshi Shigehara

Chikahiro Hori

Tetsuyo Shigehiro

Yoshimitsu Itoh

Yasoji Suzuki

Isao Abe

Yukihiro Saeki

Osamu Matsumoto

Hiroyoshi Murata

Takaya Kitahara

Takuma Aoyama

Takumi Tsukazaki

Shigeru Hiura

Shinji Inada

Ryouichi Isohata

Kiyoyasu Shibata

According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Level shift switch and electronic device with the same

A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

CMOS logic integrated circuit

A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with the electric potential of the second terminal.

Bus switch with level shifting

A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data signal into the data communication path, and has a buffer amplifier section for compensating the data signal.

Semiconductor device and electric apparatus

The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of Pand Nwhose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P. The level shifter includes second and third inverters which are interposed between an output of the first input buffer and the second terminal and which use the high power voltage and which are connected in series, an output of the first input buffer is supplied to an input of the second inverter and an output of the third inverter, and a circuit threshold value of the second inverter using the high power voltage is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage. A first logic circuit for calculating the signal of the low or high power voltage is disposed in a certain portion of the signal path, and a circuit threshold value of the first logic circuit is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage.

Signal level conversion circuit

A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer. The bus-hold circuitry may have one bus-hold circuit between the switching transistor and the output terminal, for one-way signal transfer. These circuit arrangements offer reduced chip size and simplified control operations for accurate output-terminal voltages. Moreover, the arrangements omit one direction-switching terminal in two-way signal transfer.

Signal-level converter

A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Switch circuit

A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal. The circuit also includes a first n-channel MOS transistor having a third gate, a third source, a third drain and a second back gate, in which the third gate, in which the third source and the second back gate of the first n-channel MOS transistor are connected to the reference terminal, and including a second n-channel MOS transistor having a fourth gate, a fourth source, a fourth drain and the second back gate, in which the fourth source of the second n-channel MOS transistor are connected to the third drain of the first n-channel MOS transistor, and the fourth gate and the fourth drain of the second n-channel MOS transistor are connected to the power supply terminal.

Protection circuit provided in semiconductor circuit

A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption.

Logic circuitry-implemented bus buffer

A temperature detector circuit for converting a forward drop voltage of a diode to digital data by means of an AD converter is provided. In order to restrict an occurrence of an output error caused by dispersion in diode manufacture, correction data according to digital data obtained by the AD converter is stored in advance in a storage circuit under a known arbitrary temperature condition, and subtraction is performed between digital data obtained by the AD converter under an unknown temperature condition and correction data read from a storage circuit, thereby to perform correction.

Temperature detector circuit having function for restricting occurrence of output error caused by dispersion in element manufacture

A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor region, the connecting portion having a higher resistance than those of the first and third semiconductor regions; a first electrode formed so as to be electrically connected to the third semiconductor region; and a second electrode formed so as to be electrically connected to the second semiconductor region. Thus, it is possible to prevent the element characteristics from deteriorating even if a surge voltage is applied and to decrease the element size.

Semiconductor device

An auto-clear circuit which has a switch device connected between a power supply voltage terminal and first and second nodes, and a potential division device, connected between the first node and a ground terminal, for outputting a first potential obtained by dividing a potential of the first node. Also included is a charge/discharge device, connected between the second node and a ground terminal, for charging or discharging the second node on the basis of the first potential output from the potential division device, and a latch device for holding a potential of the second node to output a signal from an output terminal, and supplying the signal to the switch device to control an opening/closing operation.

Auto-clear circuit and integrated circuit including an auto-clear

The present invention provides a feedback control circuit for controlling the operation of an sense amplifier circuit in accordance with the feedback of an output signal to the AND array, for a PLD having an ITD circuit. The feedback control circuit includes a storage element for storing data as to whether or not an output signal is fed back to the AND array, and a read-out circuit for reading out the data of the storage element. With the data read out from the storage element, a pulse signal output from the ITD circuit for detecting a change in the output signal is supplied to the sense amplifier circuit so as to set it in an enable state when the output signal is fed back to the AND array, and the supply of the pulse signal to the sense amplifier circuit is inhibited so as to set it in the disable state when the output signal is not fed back to the AND array.

Growing community of inventors

Kanagawa, Japan

Akira Takiba