Fujitsu Corporation

Akira Takei

Kunihiko Wada

Ryoiku Togei

Takashi Miida

Yoshihiko Hika

Tetsuo Nishikawa

Eiichi Nagai

Teruyuki Nabeta

Kiyoshi Tashiro

Field isolation between arrayed picture cells of an image sensor is fabricated thinner than the insulation layer for the peripheral portion of CCD operatively connected to picture cells. The field isolation is fabricated by a selective thermal oxidization, by which the isolation film inflates not only vertically but also laterally, therefore the thinner isolation layer can be narrower. And, the lower applied voltage to the picture cell than applied voltage to the CCD portion allows the narrower isolation. The narrower field isolation between the picture cells allows greater density of integration of the picture cells. Procedures to embody the invention are disclosed, one of which is to fabricate the thinner isolation first, and another one is the thicker insulation layer first.

Image sensor

An image sensor includes a plurality of potential monitoring transistors connected to respective floating electrodes for separately monitoring changes in potential of the respective floating electrodes. In addition, the image sensor includes an output circuit for producing an output signal which varies in accordance with one of the monitored potentials which is one of the highest potential and the lowest potential.

Image sensor having charge storage regions

An image sensor includes charge storage regions which gradually store charges corresponding to the amount of light received, a plurality of image transfer elements which gradually transfer the charges, and transfer gates which transfer the charges in the charge storage regions to the charge transfer elements. The image sensor provides further a device which changes an electric potential of an electrode of the charge storage regions in accordance with the amount stored of the charges, and a device which detects the electric potential of the electrode and outputs the detected electric potential as a switchover timing control signal of the transfer gates.

A nonvolatile semiconductor memory device including at least one memory cell which comprises a floating-gate, a control gate and a single impurity diffusion region formed exclusively for the memory cell. In this device, a small depletion region and a large depletion region due to the charged and discharged state of the floating-gate represent the information '1' and '0'.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device of a floating-gate type comprises a floating-gate and two control gates. The floating-gate is divided into two conductive regions having a conductivity type opposite to each other. A first control gate is placed above a first region and a second control gate is placed above a second region. In this device, the erase operation is performed by causing avalanche breakdown within the floating-gate.

In a semiconductor memory device of the present, due to a heavily doped region formed on the semiconductor substrate, the depletion layer does not spread deeply toward the interior of the semiconductor substrate. In addition, a capacitor is formed by the heavily doped region, an insulating film formed on this region and a semiconductor layer formed on this insulating film. As a result, variation of capacitance of the capacitor due to .alpha.-ray particles is low. Furthermore, information is stored in the semiconductor layer which is formed above the semiconductor substrate so that the occurrence of a soft error is minimized.

Semiconductor memory device

A semiconductor memory device, which comprises: a P-type semiconductor material comprising on the surface thereof, an N-type doped layer, one surface region of the substrate adjoining the doped layer being used as a gate region, and further comprising in the interior thereof an N-type buried layer below another surface region of said substrate adjoining said one surface region. Electric charges representing information are stored in the buried layer. The reading time and the refreshing period are improved by shortening said reading time and lengthening said refreshing time utilization of said N-type buried layer.

A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.

A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consist of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. The resistive layer is formed by utilization of a two stage deposition of the polycrystalline silicon layer with appropriate masking steps.

Growing community of inventors

Yokohama, Japan

Akira Takei