Ricoh Company, Ltd.

Akira Takata

Koichi Fujii

Shigeki Matsuoka

Takeo Obata

Takuro Fujioka

Toyofumi Takahashi

A programmable logic device includes wordlines each having two sides for connection, bitlines substantially intersecting with the wordlines constituting an AND array portion in conjunction with the wordlines and a plurality of nonvolatile memory elements. Each nonvolatile memory element has data memorized therein and is connected to one of the wordlines and one of the bitlines. And the device has an OR array portion which conducts a predetermined calculation on the basis of the data read from the memory element, an input buffer circuit connected to one side of the wordlines and a decoder connected to the other side of the wordlines through a wordline driver.

Programmable logic device

A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device. In a still further form, the AND plane further includes a plurality of test input lines each associated with the corresponding one of the product term lines of the AND plane, and an three-state output buffer is connected between the OR plane and a device output terminal, whereby the output buffer is enabled by a logical sum between a selected product term from the AND plane and an internally supplied test mode signal.

Programming logic device with multiple independent feedbacks per

A logic integrated circuit device includes a pair of input terminals, an OR gate having a pair of inputs coupled to the pair of input terminals, an exclusive OR gate having a pair of inputs coupled to the pair of input terminals, a first output terminal connected from one of the pair of input terminals through a first gate switch and also from the output of the OR gate through a second gate switch, and a second output terminal connected from the other of the pair of input terminals through a third gate switch and also from the output of the exclusive OR gate through a fourth gate switch. Also provided is a data read out circuit which is operatively coupled to the four gate switches through a switch control circuit. Depending on the condition of the data read out circuit, either one of one of the pair of input signals and a logical sum signal between the pair of input signals is output at the first output terminal and either one of the other of the pair of input signals and an exclusive logical sum signal between the pair of input signals is output at the second output terminal.

Logic integrated circuit device selecting as outputs any two of two

Programming logic device with test-signal enabled output

A programmable logic device include an AND gate array and an OR gate array, at least one of which is programmable by the user. The AND gate array includes a plurality of input lines, a plurality of product term lines which cross said plurality of input lines, and a plurality of programmable elements located at the intersections between the input and product term lines. An activation control circuit is also provided for activating at least one of the product term lines while keeping those product term lines which are not used for programming deactivated. With this structure, the waste of power can be minimized.

Partially enabled programmable logic device

A programmable logic device of a single semiconductor chip includes a plurality of programmable AND-OR logic blocks, each block including an AND gate array and an OR gate array and at least a pair of input and output lines; a plurality of input/output buffer blocks, each block including at least one input and output lines; and a plurality of interconnection lines across which the input and output lines extend. A programmable switch is provided at each of the intersections between the input and output lines and the interconnection lines, so that each of the input and output lines are selectively connected to a desired one of the interconnection lines. Preferably, each of the interconnection lines further includes at least one programmable switch so that each of the interconnection lines may be divided into a desired number of segments which are electrically isolated from one another. A programmable logic device may include a plurality of programmable logic unit cells and first interconnecting means for interconnecting the cells, each of the cells including a plurality of programmable AND-OR logic blocks, a plurality of input/output blocks and second interconnecting means for interconnecting the blocks.

Programmable logic device having plural programmable function cells

A power supply switching circuit for supplying a pair of power supply voltages different in level, such as programming voltage V.sub.pp and reference voltage V.sub.cc, selectively is provided. The circuit includes a plurality of P-channel and N-channel MOS transistors which are appropriately connected such that no leakage or reverse current is produced even if the voltage at the V.sub.pp terminal becomes lower than V.sub.cc.

Power supply switching circuit

An EPROM memory device includes a plurality of reprogrammable memory cells arranged in the form of a matrix and a test circuit capable of having two or more memory cells selected for operation at the same time during the test mode, to thereby reduce the required testing time significantly.

EPROM memory device having a test circuit

A voltage level converting circuit for use in semiconductor devices including memory such as ROMs, PROMs and EPROMs comprises an input terminal to which an input signal is applied, a voltage level detecting circuit for detecting the voltage level of the input signal received by the input terminal and supplying an output signal of the voltage level determined in response to the level of the input signal, an inverter connected to the voltage level detecting circuit and a CMOS device having a pair of outside source/drain terminals connected between the input terminal and a first reference voltage, a gate terminal connected to the output of the inverter and the inner interconnected source/drain terminals connected to an output terminal of the circuit.

Growing community of inventors

Toyonaka, Japan

Akira Takata