Hitachi, Ltd.

Akira Takagishi

Takuya Mizokami

Masahiro Takasago

Toru Kawashima

Masanori Matsuzaki

Noritaka Narita

Toshiharu Kon

A PLL circuit produces a synchronous signal by utilizing a regenerative clock signal in a VFO portion in a regenerative signal which was read out from a recording medium in sections. When a defective portion is present in a regenerative clock signal, the same sector is read out again from the recording medium to obtain the regenerative signal. A loop gain of the PLL circuit is made to be low in the defective portion of the regenerative signal which was read out again, thereby to prevent the synchronous fault of the PLL circuit due to the defective portion.

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Fujisawa, Japan

Akira Takagishi