International Business Machines Corporation

Other

Kabushiki Kaisha Toshiba

Akira Sudo

Rajarao Jammy

Byeong Yeol Kim

Rama Divakaruni

Jack Allan Mandelman

Oleg Gluschenkov

Ramachandra Divakaruni

Jochen C Beintner

Johnathan E Faltermeier

Philip L Flaitz

Mihel Seitz

Carol J Heenan

Yoichi Takegawa

Jeffrey P Gambino

Carl John Radens

Herbert Lei Ho

Ulrike Gruening

Akihiro Nitayama

Kazumasa Sunouchi

Dirk Tobben

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Pitcher-shaped active area for field effect transistor and method of forming same

A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape. At least one of the plurality of the strap conductors is contiguous with a corner of the trench, and the plurality of strap conductors comprises a first strap conductor and a second strap conductor and the conductor is contiguous with the first strap conductor and the second strap conductor such that the second strap conductor and the conductor form an L-shape.

Low resistance strap for high density trench DRAMS

A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Pedestal collar structure for higher charge retention time in trench-type DRAM cells

Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.

Collar process for reduced deep trench edge bias

A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region. Thus, it is possible to improve the charge holding characteristic of a memory cell without deteriorating the performance of a cell transistor.

Semiconductor memory device and method for producing same

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Poughkeepsie, NY, United States of America

Akira Sudo