Sony Corporation

Akira Shirahama

Shinichiro Miyazaki

Takeshi Ono

Nobuo Ueki

Takeshi Ohno

Shinichirou Miyazaki

Takahiko Tamura

Hiroyuki Kojima

Yoshiki Shirochi

Hitoshi Nakamura

Hiroshi Murayama

Ken Tamayama

Hiroshi Yamagata

Jun Ueshima

Hiroshi Sugaya

Yoshinobu Tsunetomi

Kazuhiko Fujihara

Masayuki Miyagawa

Yumiko Mito

Seigo Hirakawa

Nobou Ueki

Toshinari Fuchigami

A display image correcting device including, retaining section configured to retain reference correction amount data for correcting nonuniformity as a predetermined factor of an image displayed on a basis of a video signal, the reference correction amount data representing an amount of correction at a predetermined horizontal and vertical position of the image, the amount of correction being obtained in correspondence with a video signal level as a reference, and correcting section configured to perform correction processing on the video signal in correspondence with a horizontal direction and a vertical direction of the image, and a brightness direction, and performing the correction processing on a basis of three-dimensional correction amount data obtained by making two-dimensional correction amount data corresponding to a horizontal and vertical position, the two-dimensional correction amount data being obtained on a basis of the reference correction amount data, linearly proportional or nonlinearly proportional to level of the video signal to be corrected.

Display image correcting device, image display device, and display image correcting method

An information-processing device receives and processes predetermined program data. The information-processing device includes an extracting unit for extracting image data and audio data of a program selected by a user, an obtaining unit for obtaining information related to the selected program, and a setting unit for setting a control parameter for controlling an image data display or an audio data output of the selected program in accordance with the related information.

Apparatus and method for processing predetermined program data

Viewing of a program is enabled at optimum image quality. A correspondence table of an image signal processing parameter and a combination of TMCC information and transmission errors is stored in a RAM. A CPU reads out an image signal processing parameter corresponding to a combination of TMCC information supplied from an IF demodulator and transmission errors supplied from the IF demodulator, a demultiplexer and an MPEG video decoder from the correspondence table stored in the RAM, and controls signal processing in an image signal processing portion and display processing in an image display portion based on the image signal processing parameter.

Image processing apparatus and method, and recording medium

Viewing of a program at optimum image quality is realized. A correspondence table of combinations of MPEG video encoding parameters and image signal processing parameters is stored in a RAM. A CPU reads out from the RAM an image signal processing parameter corresponding to a combination of MPEG video encoding parameters supplied from a demultiplexer, and on the basis of the image signal processing parameter, controls image signal processing in an image signal processor.

Image processing apparatus, method, and recording medium for controlling image quality

According to the signal processing apparatus of the present invention, in a text signal processing circuit, predetermined signal processes are executed to a luminance signal Y and color difference signals U and V in which a ratio of sampling clocks is equal to (4:4:4) and resultant signals are supplied to a mixing circuit. In a video signal processing circuit, predetermined signal processes are executed to the signals Y, U, and V in which a ratio of sampling clocks is equal to (4:1:1) or (4:2:2). The signal Y is supplied to the mixing circuit through a delay adjusting circuit and the high frequency components are removed from the signals U and V by a band limiting filter and, after that, the resultant signals are supplied to the mixing circuit. The signal mixed by the mixing circuit is supplied to a LPF through a D/A converter. In the LPF, the signal is demodulated by the band limiting filter according to (4:4:4).

Signal processing apparatus

The invention provides an image processing apparatus and method as well as a providing medium by which deterioration of the vertical resolution is prevented and conspicuous appearance of line flickering is suppressed. In order to convert an interlaced video signal having 525 scanning lines into another progressive video signal having 525 scanning lines while maintaining the image size, in an odd-numbered field, a line after conversion is offset by 0.5 H (H is the distance between horizontal scanning lines of the inputted video signal). Consequently, pixel data of each line Oi are produced from pixel data of two lines Ii and Ii&plus;1 before conversion. As a result, pixels of a line on the boundary between white pixels and black pixels have a gray color. In an odd-numbered field, no offset is given, and pixel data of each line I of the field before conversion are set as they are as pixel data of each line Oi of the field after conversion. The pixels of the line on the boundary between the white and black pixels become white or gray pixels, and consequently, when compared with an alternative case wherein such pixels on the boundary line are white and black pixels, line flickering is prevented from being observed conspicuously on a display screen.

Image processing apparatus, method and providing medium

There is provided delay means for allowing a delay difference to be provided between the timing of image size information which is set into writing side memory control means and the timing of image size information which is set into reading side memory control means in a manner such that the image size when data is written into first and second field memories and the image size when the data is read out from the first and the second field memories coincide. The image size information is set into the writing side memory control means and the reading side memory control means so as to have a delay difference between them. The image size is set by controlling the first and the second field memories in accordance with the image size information by the writing side memory control means and the reading side memory control means. A switching control of every field is performed in a manner such that while the writing process is performed to one of the field memories, the reading process is performed to the other field memory.

Image processing apparatus, image processing method, and television receiver

A picture processing apparatus for picture-in-picture applications where the number of pixels n in the horizontal direction of an original picture, the number of pixels m in the vertical direction thereof, the number of pixels N in the horizontal direction of the converted picture, and the number of pixels M in the vertical direction thereof are supplied to a dividing device. Thus, ratios A&equals;N/n and B&equals;M/m are obtained. The inverse number 1/A of the value A is cumulated by circuits. An address generating circuit generates addresses at four points for calculating a density value a of a converted pixel corresponding to the integer part of a cumulated value &Sgr;(1/A). These addresses are supplied to memories. The pixel data at the four points that are read from the memories are supplied to respective multiplying devices. The decimal part of the value &Sgr;(1/A) is supplied as an interpolating coefficient p to a multiplying device. A coefficient (1&minus;q) is supplied to a multiplying device. Likewise, in the vertical direction, coefficients q and (1&minus;q) are supplied to respective multiplying devices. These multiplying devices and adding devices perform operations. Thus, the density value a of the converted pixel is obtained and supplied from a terminal.

Apparatus and method for enlarging/reducing a video picture size

In a divider, a ratio of a magnification or a reduction of an image is set from a writing range and a reading range. In a horizontal interpolating circuit and a vertical interpolating circuit, an interpolation is performed on the basis of the magnification ratio. In the horizontal interpolating circuit and the vertical interpolating circuit, an interpolation is performed on the basis of the reduction ratio. In a field memory, a portion of the image of an arbitrary size at an arbitrary position is written on the basis of a control signal which is supplied from a write memory control circuit. The image is read out from the memory on the basis of a control signal which is supplied from a read memory control circuit.

Television apparatus, display method of television apparatus and picture plane control apparatus, and method

An interpolation interval V,obtained by the picture sizes of the original picture and the converted picture is cumulated by an adder. In the odd field, a selector selects &lsqb;0.5&rsqb; as an offset corresponding to an odd/even field determination signal. In the even field, the selector selects &lsqb;0&rsqb; as an offset corresponding to the odd/even field determination signal. In a vertical blanking interval, the offset is selected as an output. Thus, in the odd field, the offset value &lsqb;0.5&rsqb; is added to the cumulated value of V,. Thereafter, V,is cumulated again. Corresponding to the cumulated value, a line read address n and linear interpolating coefficients q,and q,are obtained. When V,is cumulated, offsets corresponding to the scanning start points in the odd field and the even field are added. Thus, the interlace accuracy is kept.

Picture processing apparatus and processing method

When an image size is changed by using a linear interpolating process, a picture quality is improved so as not to overlap the position of an original signal and the position of an interpolation signal. An interpolation interval Vdp which is derived from an original image and an image size after the conversion is stored into a register of an input side and is accumulated and added by an adder from a register of an output side through a selector. A predetermined calculation is performed and an offset value q.sub.0 is obtained in a circuit. The value q.sub.0 is selected by the selector and the register of the output side is initialized for a vertical blanking period. Thus, a value (.delta.+nVdp) in which the value q.sub.0 was added to the accumulation value of Vdp is derived. On the basis of the value (.delta.+nVdp), a read address (n) of the original image and linear interpolation coefficients q.sub.n1 and q.sub.n2 are obtained. A similar process is also executed for the horizonal direction and an address (m) and coefficients p.sub.n1 and p.sub.n2 are obtained. A proper offset value is added to the interpolating position and the picture quality can be improved without overlapping the original signal and the interpolating position.

Image processing apparatus and processing method

A picture processing apparatus and method for enlarging and reducing a picture wherein when a picture is reduced, horizontally adjacent pixel data is supplied from a delaying device to a horizontally interpolating circuit. With the pixel data, a coefficient p and a 1's complement (1-p) thereof supplied from an interpolation coefficient circuit, an interpolating process in the horizontal direction is performed. In addition, a pixel at the position of p=1 is thinned out. Pixel data that has been interpolated in the horizontal and vertical directions and that has been thinned out is written to a memory. When a picture is enlarged, pixel data that is read from a memory is delayed by two line memories and two adjacent pixels are properly selected by a switch circuit. A vertically interpolating circuit performs an interpolating process in the vertical direction. When pixel data is read from the memory, particular pixel data is read twice depending on a magnification. In the horizontal direction, likewise, an interpolating process is performed in the similar manner and an enlarging process is performed.

In a CRT display and a television set having the same, horizontal/vertical synchronizing signals are separated from a video synchronizing signal in a synchronizing separation circuit, and position information S of a vertical frame is generated on the basis of the horizontal/vertical synchronizing signals in a count-down processor and then converted to corrected vertical frame information W in a function circuit to output a vertical deflection waveform signal and a horizontal deflection correcting waveform signal. Further, the corrected vertical frame information W is compared with predetermined voltages in comparators to detect an effective frame range in the vertical direction.

Cathode ray tube display and television set having the same

A multi-system video signal demodulating apparatus includes at least a color signal processing unit and a color discriminating function for demodulating a component video signal from video signals of two or more different systems. The multi-system video signal demodulating apparatus includes a detector for detecting continuity between vertical synchronizing signals of the input video signals. The color discriminating function is executed when the detector detects a discontinuity between the vertical synchronizing signals. The continuity between the vertical synchronizing signals of the input video signals is detected. The color discriminating function is executed when a discontinuity between the vertical synchronizing signals is detected during continuity detection. A synchronizing signal of an input video signal is discriminated. A frequency of a color burst signal is discriminated based on a result of the synchronizing signal discrimination. The color burst discrimination is executed or stopped based on a result of the color burst discrimination. An amplitude of the color burst is discriminated based on a result of the synchronizing signal discrimination. A phase of the color burst is discriminated based on a result of the amplitude detection. A television system of the video signal is discriminated based on a result of the phase detection. An oscillation frequency of the crystal oscillator is discriminated based on a discriminated result of the television system discrimination.

Multi-system video signal demodulating apparatus

A vertical deflection control circuit includes a double-speed counter (18) for counting a clock with a frequency of 2f.sub.H, f.sub.H representing a horizontal frequency of an inputted video signal, in synchronism with a vertical sync signal, timing generating means (20) for judging even-field/odd-field of the input video signal and generating a timing signal based on a judged result, and offset signal adding circuitry (28) for adding an offset value to an output of the double-speed counter (18) at a timing of the timing signal, thereby a video signal in a vertical deflection system can be double-scanning-converted with a simple arrangement.

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Kanagawa, Japan

Akira Shirahama