Analog Devices,inc.

Analog Devices International Unlimited Company

Akira Shikata

Abhishek Bandyopadhyay

Junhua Shen

Keith Anthony O'Donoghue

Daniel Peter Canniff

Anping Liu

Shaolong Liu

Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

Enhancing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters

An excess loop delay compensation (ELDC) technique for use with a successive approximation register (SAR) based quantizer in a continuous time delta-sigma ADC is described. The techniques can efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers. An ELDC circuit can include a charge pump having a digitally programmable capacitance to adjust a gain, such as the gain of the ELDC digital-to-analog converter (DAC) or the gain of the SAR DAC.

Gain programmability techniques for delta-sigma analog-to-digital converter

The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

Multi quantizer loops for delta-sigma converters

Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.

Method to embed ELD DAC in SAR quantizer

A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.

Analog-to-digital converter speed calibration techniques

Improvements in analog-to-digital converter (ADC) circuit accuracy are described that can utilize a digital-to-analog converter (DAC) circuit with one or more redundant unit elements, or one or more bits redundancy or non-binary weighted capacitors, and can reuse the existing DAC circuit for noise reduction to save power and die area. An ADC circuit can use redundancy bit(s), e.g., one or more DAC unit elements of a main DAC, and the remaining lower bits of the main DAC for repeated bit trials, and can average the data from the repeated bit trials to suppress noise from conversions.

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Everett, MA, United States of America

Akira Shikata