Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Semiconductor Software Corporation

Akira Okugaki

Kenji Kohda

Hiroyasu Makihara

Tomoshi Futatsuya

Shinichi Mori

Masahide Kaneko

Kenji Koda

Akiko Motoshima

Hiromi Sadaie

In a flash memory, a reading bit line and a writing bit line are provided corresponding to a respective column of memory cells. A well voltage and a voltage on a source line can be controlled for each sub-block. Accordingly, data can be read at a sub-block while data can be written/erased at another sub-block, and therefore, the capacity ratio of a back ground operation region to the main memory region can be changed as desired.

Non-volatile semiconductor memory device having a back ground operation

A semiconductor device having a multi-value memory including an offset ROM and a manufacturing method thereof can be obtained which allows accurate formation of a source/drain region and an offset region. In this semiconductor device, an offset source/drain region is provided so that a side end portion thereof is positioned substantially in flush with a lower end of an external surface of a sidewall insulating film placed on a side surface of a first gate electrode. Consequently, the offset source/drain region can be formed easily in a self-aligned manner by ion implantation using the sidewall insulating film as a mask, thereby forming the offset region accurately in a self-aligned manner.

Semiconductor device having a mask programmable memory and manufacturing

A mask ROM device includes a plurality of memory cells each having an enhancement type FET having a gate electrode and first and second source/drain regions, a plurality of word lines connected to the gate electrodes, a plurality of bit lines connected to the first source/drain regions, a connection line formed above the gate electrode so as to electrically connect the first and second source/drain regions through contact holes in each of memory cells selected according to information to be stored.

Mask ROM device

A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on different rows and different columns in this memory cell array. Data are simultaneously read from the simultaneously selected memory cells. The simultaneously read data include information bits and at least one error checking bit. Only data of a 1-bit memory cell is read from one word line at the maximum. Thus, it is possible to extremely reduce a probability that two or more erroneous data bits are included in a plurality of bits of simultaneously read data even if a selected word line is defective. It is possible to execute error checking and correction in accordance with an ECC scheme, improving repairability for defective bits in a semiconductor memory device.

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Hyogo, Japan

Akira Okugaki