Fujitsu Corporation

Pfu Limited

Akira Naruse

Kohta Nakashima

Kouichi Kumon

Mitsuru Sato

Masahiro Miwa

Naoto Fukumoto

A core executing processes in plural threads specifies one gate to read out a state of the gate from a thread progress control unit holding information of plural gates disposed in a loop state, setting a state of a gate disposed subsequently relative to a gate when a state of the gate is set to a first state to a second state, and setting the state of the gate to the first state when a certain period of time elapses from a first request of reading the state for the gate which is set to the second state, by every certain process in each thread. The core executes a next process when the state of the specified gate is the first state, and makes the execution of the next process wait until the state becomes the first state when it is not the first state.

Processor and control method of processor

A node includes a sending unit that sends a signal to another node; a receiving unit that receives a signal from another node; a determining unit that determines, when the sending unit sends a signal to the other node, that synchronization has been established with the other node, that determines, when the receiving unit receives a signal from another node, that synchronization has been established with the other node, and that determines, when a node in which synchronization has already been established with the other two nodes in each of which synchronization has been established, that synchronization has been established with the nodes; and a selecting unit that selects an information processing apparatus that is not determined, by the determining unit, that synchronization has been established as the other node at the sending destination for the signal.

Information processing system and control method of information processing system

The present invention includes a plurality of computing units executing a plurality of threads including a communication control thread to which a receiving process by polling is assigned. In a CPU core, a computing unit executing the communication control thread performs polling in a memory region indicating notification of arrival of data and waits for execution of the receiving process until arrival of data, and when a computing unit executing an application thread executes a process assigned to the application thread, the computing unit executing the communication control thread moves to a resource-saving mode in which the use of physical resources is suppressed.

Information processing device and method for controlling information processing device

An information processing apparatusincludes a memorythat stores information used for arithmetic processing. The information processing apparatusincludes a CPUthat operates arithmetic processing by using the information stored in the memory. The information processing apparatusincludes a measuring unitthat measures power consumption of the memory. The information processing apparatusincludes a CPU frequency controlling unit setting unitthat sets an operating frequency of the CPUaccording to the power consumption measured by the measuring unit

Dynamically adjusting operating frequency of a arithemetic processing device for predetermined applications based on power consumption of the memory in real time

A port number is stored in a memory in association with one or more addresses using a data block by which at least one port number associated with a predetermined number of consecutive addresses is written into the memory. Further, a first port number assigned to output ports each being provided for different one of a plurality of relay nodes is stored in association with first consecutive addresses in such a manner that one or more data blocks including the first port number associated with the first consecutive addresses are written into the memory.

Apparatus and method for storing a port number in association with one or more addresses

A prohibition turn determination apparatus determines an initial path so that the communication amounts of respective links connecting switches to each other are most efficiently distributed between a communication pair, that is, a pair of servers communicating with each other via a network. Then, the prohibition turn determination apparatus calculates the communication amounts of respective turns formed along the initial path based on the communication amounts set between end nodes which are the communication pair. Next, the prohibition turn determination apparatus determines prohibition turns, which are not used for packet communication, based on the communication amounts of respective turns by an Up/down method or a TP method. Finally, the prohibition turn determination apparatus determines the final routing to avoid the prohibition turns.

Prohibition turn determination apparatus

A computer acquires correspondence data including a plurality of combinations of identifiers of selected computers, in which parallel processes are started, and identifiers of the parallel processes, wherein the selected computers are among a plurality of computers connected to a multipath network having relay devices extending over two or more hierarchies. The computer specifies a network identifier to be used for distributing communication paths among the selected computers for every selected computer that includes an identifier in the correspondence data, wherein the specified network identifiers is among network identifiers of respective communication paths in the multipath network, and the specified network identifier corresponds to each identifier of a plurality of computers, and is used for routing.

Recording medium storing communication program, information processing apparatus, and communication procedure

First-stage switches (Bto B), second-stage switches (Mto M), and third-stage switches (Tto T) include a bottom connection path that configure to interchange a connection point of one or more second signal transmitting units and a connection point of another one or more second signal transmitting units, in a Fat Tree configuration between the first-stage switches (Bto B) and the second-stage switches (Mto M) constituting a one-set Fat Tree with the third-stage switches (Tto T).

Network apparatus and network managing apparatus

An initial address allocating unitallocates a predetermined address to each of the nodesconnected to respective first stage switches. A connecting state acquiring unitacquires a connecting state from each of the first stage switches, each of second stage switchesand each of third stage switches. An erroneous connection detecting unitcompares the connecting state acquired by the connecting state acquiring unitwith a prestored predetermined connecting state, thereby detecting an erroneous connection. An address changing unitchanges an address of the nodeallocated by the initial address allocating unitto satisfy a first predetermined condition based on the connecting state, when the erroneous connection is detected by the erroneous connection detecting unit

Network managing device and network managing method

In response to an all-to-all inter-process communication request from a local process, a computer repeatedly determines a destination server in accordance with a destination-server determination procedure so that, in a same round of destination-server determinations repeatedly performed by the respective servers during all-to-all inter-process communication, the servers determine servers that are different from one another as destination servers. Each time the destination server is determined, the computer sequentially determines a process running on the determined destination server as a destination process. Each time the destination process is determined, the computer obtains transmission data for the destination process from a send buffer in which the transmission data is stored as a result of execution of the local process and transmits the obtained transmission data to the destination server so as to enable reading of the transmission data during execution of the determined destination process in the destination server.

Computer for performing inter-process communication, computer-readable medium storing inter-process communication program, and inter-process communication method

A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread.

Processor and arithmatic operation method

This method includes: obtaining first data including identifiers of selected computers for invocation of parallel processes among plural computers connected to lowest-layer relay apparatuses in a network including relay apparatuses in plural layers, wherein the network includes paths between a relay apparatus in a first layer and plural relay apparatuses in a second layer that is an immediately upper layer than the first layer; and selecting, for each of the selected computers and from network identifiers for respective communication routes, network identifiers to be used for communication with other selected computers so as to avoid coincidence of communication routes between the selected computers for which a same difference value is calculated between identification numbers, wherein the network identifiers are associated in advance with an identifier of each of the plural computers and are used for routing in the network, and the identification numbers are assigned for ordering the selected computers.

Communication technique in network including layered relay apparatuses

An instruction trace of a first instruction string is generated from a second instruction string obtained by sampling, at predetermined intervals, the first instruction string. The second instruction string is divided into partial instruction strings. A combination of the partial instruction strings is selected based on the similarity of stored partial instruction strings. A plurality of combination patterns are generated by combining instructions included in the selected partial instruction strings. A likelihood is calculated for each of the combination patterns, and the combination patterns are stored in the storage unit based on the likelihood.

Instruction-trace generation program, instruction-trace generating device, and instruction-trace generating method

An apparatus for controlling devices for searching homology of queries in a base sequence in parallel, includes: a memory for storing a base sequence and an appearing frequency of each of first strings each having a fixed length appearing in the base sequence; and a processor for executing a process including: obtaining queries for searching homology in the base sequence; retrieving each of second strings each having a longer fixed length then that of first strings and partially appearing in each of the queries; determining an approximate appearing frequency of each of the second string on the basis of the appearing frequency of the first strings; evaluating for each of the query sequences a load of task for searching homology; and allocating each task for searching homology for each of the queries among the devices on the basis of the result of evaluation of the load of the each task.

Homology searching method

A computer has a plurality of processors with a cache memory. When a spinwait detecting unit provided to a processor detects execution of a spinwait command, it instructs monitoring of a variable value as a spinwait end condition and changes an operating state of a processor. A value change detecting unit provided to the cache memory monitors the variable value specified by the spinwait detecting unit, and when it detects that the variable value is changed, it posts the value change to the processor so as to return the operating state into its original state.

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Kawasaki, Japan

Akira Naruse