Sony Corporation

Akira Nakagawara

Hideaki Kuroda

Kenshiro Arase

Yoshiaki Hagiwara

Michitaka Kubota

Kazuo Watanabe

Ichiro Fujiwara

Katsuya Nakashima

Akihiko Hashiguchi

Shumpei Kohri

Akihiro Uda

A nonvolatile semiconductor memory device enabling a high sensitivity read operation by a low voltage, provided with a gate insulating film comprised of a bottom insulating film, a charge storing film, and a top insulating film successively stacked from the bottom, the bottom insulating film including a silicon oxynitride film directly under the charge storing film, and reading a bit of data stored at a local portion of a sub-source line side of a memory transistor and a bit of data stored at a local portion of a sub-bit line side independently by the reverse read method, whereby the incubation time is suppressed by the presence of silicon oxynitride, the controllability of the thickness of the charge storing film is improved, and the threshold voltage in an erase state is decreased, and a method of high sensitivity reading whereby a lower voltage and improved operational reliability are achieved.

Apparatus and method for high sensitivity read operation

A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an opening reaching the impurity region, and a second insulating film and a second semiconductor layer of a second conductivity type stacked in the opening.

One time programmable semiconductor nonvolatile memory device and method for production of same

A flash EEPROM, wherein provision is made of an auxiliary bit portion connecting nonvolatile memories in parallel with bit lines of a memory array portion and a spare row decoder for controlling addresses of a redundant memory portion, which records the cumulative number of cycles of rewriting and erasure for each word line in the nonvolatile memories, judges from the stored cumulative number of cycles if the number of cycles of a sector has reached a limit value, and, when reaching it, replaces the word line with a redundant word line so as to prolong the life of the memory even when the cumulative number of cycles of a specific word line has reached a limit value and which stores the data in accordance with different phases when the number of the data '1' or '0' is greater than or less than a predetermined number at the time of writing data and fetches the stored information based on the phase information at the time of reading data so as to reduce the drain disturbances.

Nonvolatile semiconductor flash memory

A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Semiconductor memory device with address transition detector

A dynamic random access memory, in which a connection switch circuit is provided between the output of a sense amplifier and a data bus or between memory block, which circuit is controlled in accordance with a write/read control signal of data so as to enable the bit line signal to be read at a high speed and the layout area of the IC to be reduced.

Dynamic random access memory

A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the HIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively. Since the bit lines and the column lines may be used fixedly, the second and the third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration. The MIS transistor constituting the memory cell may be of such a construction in which the source and drain regions may be provided below the thick insulating film formed on the substrate surface, such as field oxide film. This results in more effective utilization of the area on the substrate to realize a higher degree of integration. The self-alignment process promotes the circuit integration more effectively.

Read-only memory device

A non-volatile memory comprises memory cells M arranged in a matrix (MB), word lines (W1 to Wn) for row selection, sub-bit lines (B: B12, B21, B22, B31), sub-column lines (C: C11, C12, C22), a column selection circuit 1, a bit line selection circuit 2, and a column line selection circuit 3. The word lines (W1 to Wn) are used as gates common to the rows of the memory cells M, a group of sub-bit lines B and sub-column lines C is selected by the column selection circuit 1, an even-numbered or odd-numbered sub-bit line B is selected from each group and connected to any one of main bit lines (B1, B2 and B3) by the bit line selection circuit 2, and an even-numbered or odd-numbered sub-column line (C) is selected from each group and connected to any one of main column lines (C1 and C2) by the column line selection circuit 3.

High density nonvolatile memory and decoder of the same

A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively. The second and the third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration. The MIS transistor constituting the memory cell may be of such a construction in which the source and drain regions may be provided below the thick insulating film formed on the substrate surface, such as field oxide film.

Method for producing a read-only memory having a plurality of MISFET

A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arranged alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively. Since the bit lines and the column lines may be used fixedly, the second and third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration.

Read only memory device

In a balanced differential amplifier, a constant current source MOS FET operable in an unsaturated region is usually incorporated. When noise is inputted to the differential amplifier, the current source FET undergoes an influence of noise level superposed upon the input signal DC voltage thereof, thus deteriorating the constant current characteristics. To overcome this problem, a pair of current source MOS FETs are additionally incorporated therewith. Since the two current source MOS FETs operate near a boundary between saturated and unsaturated regions and further the gate voltages applied thereto varies in out-of-phase relationship to each other in response to input signal fluctuations, it is possible to keep constant the sum total of two currents flowing through the two constant current MOS FETs, thus improving the overall constant current characteristics and therefore the suppression capability against noise inputted in phase to the amplifier.

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Kanagawa, Japan

Akira Nakagawara