Other

Kumamoto University

Tohoko University

Akira Nakada

Tadahiro Ohmi

Shigetoshi Sugawa

Tadashi Shibata

Takahisa Nitta

Tatsuo Morimoto

Naoto Miyamoto

Tatsuro Morimoto

Satoshi Sakaidani

Yoshiyuki Taniguchi

Masahiro Konnda

Masae Nakada, Legal Representative

To provide a data generating method, device, and program that can generate drawing data for drawing the entire general design graphic data with an accuracy of about 1 to 4 nm in a drawing method or a drawing system adapted to draw gradation-controllable spotlights in a two-dimensional array. The data generating method is a method for generating, in an exposure system having a function of irradiating multigradation-controllable spotlights in a two-dimensional array onto a photosensitive film on a substrate, gradation values of the spotlights based on design graphic data. Using reference data classified by features of a graphic and describing in advance combinations of gradation values mapped to coordinate information of a graphic, the method discriminates the feature in the design graphic data near positions of the spotlights and selects the combination of the gradation values in the reference data corresponding to coordinate information of the positions of the spotlights, thereby determining the gradation values.

Data generating method, data generating device, and program in an exposure system for irradiating multigradation-controllable spotlights

Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA () is stored in a memory (), the configuration management information according to information related to an instruction group, which is supplied by a configuration management unit () from the outside via a signal line group (), is read from the memory (), and the circuit configuration of the FPGA () is altered according to the read configuration management information to execute processing of the instruction group so that information processing by software is replaced by information processing by hardware in real time, which increases execution speed of information processing and shortens verification time of software, enabling software development in a shorter period and with higher efficiency.

System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit

A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.

Semiconductor arithmetic unit

There can be provided a variable function information processor in which a logic module ( ) with the further decreased number of transistors used in the logic module constituting the variable function information processor is provided, a function of being able to realize both a combinational logic circuit for-performing a full addition operation of input signals in accordance with a control signal and outputting the sum and a sequential circuit for temporarily holding the input signal to delay the signal and outputting it by the same logic module is provided, and in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits, whereby the number of elements can be further decreased, and the resources of the variable function information processor can be effectively exploited.

Variable function information processor

A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state. The first voltage and the second voltage are inputted into, respectively, the first and second input electrodes of the second MOS type transistor, and the input signal voltage is inputted into the first and second input electrodes of the first MOS transistor, and thereby, the absolute value of the difference between a voltage determined in accordance with the first voltage and the second voltage and a coupling capacity ratio between the first and the second input electrodes with respect to the gate electrode, and a voltage determined by the input signal voltage and the coupling capacity ratio is calculated.

Semiconductor arithmetic circuit

Growing community of inventors

Kumamoto, Japan

Akira Nakada